公开(公告)号：US07260491B2

公开(公告)日：2007-08-21

申请号：US11260570

申请日：2005-10-27

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F19/00

CPC分类号： G01R29/02 ,  G01R31/2884

摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.

公开(公告)号：US07245172B2

公开(公告)日：2007-07-17

申请号：US11269245

申请日：2005-11-08

申请人： David W. Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： H03L5/00

CPC分类号： H03K19/018521

摘要： A level shifter apparatus and method for minimizing duty cycle distortion are provided. The level shifter includes a bank of comparators each having an associated threshold built into it. The comparators compare a difference in source voltages for two power domains to these built-in thresholds and output a signal indicative of whether the threshold is exceeded. The output signals from the comparators are provided to a thermometric decoder which generates control signals based on these output signals. The control signals are used to control stages in a level shifter for modifying the voltage output of the level shifter. Individual stages may be enabled to thereby monotonically modify the voltage output of the level shifter and thereby decrease a time required to achieve a voltage having a level that causes a state change in a driven circuit. As a result, duty cycle distortion is minimized and maximum operational frequency is increased.

摘要翻译： 提供了一种用于最小化占空比失真的电平移位器装置和方法。 电平移位器包括一组比较器，每个比较器具有内置在其中的相关联的阈值。 比较器将两个功率域的源电压差与这些内置阈值进行比较，并输出一个指示阈值是否超过的信号。 来自比较器的输出信号被提供给基于这些输出信号产生控制信号的温度测量解码器。 控制信号用于控制电平移位器中用于修改电平移位器的电压输出的级。 单个级可以被使能，从而单调地修改电平转换器的电压输出，从而减少实现具有使驱动电路中的状态变化的电平的电压所需的时间。 结果，占空比失真被最小化并且最大的操作频率增加。

公开(公告)号：US20070081406A1

公开(公告)日：2007-04-12

申请号：US11246586

申请日：2005-10-07

申请人： David Boerstler ,  Eskinder Hailu ,  Subramanian Iyer ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Subramanian Iyer ,  Jieming Qi

IPC分类号： G11C17/18

CPC分类号： G11C17/18 ,  G11C17/16

摘要： An apparatus and method for providing a reprogrammable electrically programmable fuse (eFuse) are provided. With the apparatus and method, a pair of eFuses are provided coupled to programming current sources and sensing current sources. When the pair of eFuses is to be programmed, a first programming current is applied to a first eFuse to thereby increase the resistance of the first eFuse by an incremental amount. When the pair of eFuses is to be returned to an unprogrammed state, a second programming current source is applied to a second eFuse to thereby increase a resistance of the second eFuse to be greater than the resistance of the first eFuse. When the sensing current is applied to the eFuses, a difference in the resulting voltages across the eFuses is identified and used to indicate whether the reprogrammable eFuse is in a programmed state or unprogrammed state.

摘要翻译： 提供了一种用于提供可再编程电可编程熔丝（eFuse）的设备和方法。 利用该装置和方法，提供一对耦合到编程电流源并感测电流源的eFuses。 当要对一对eFuse进行编程时，将第一编程电流施加到第一eFuse，从而增加第一eFuse的电阻增量。 当一对eFuse将返回到未编程状态时，第二编程电流源被施加到第二eFuse，从而将第二eFuse的电阻增加到大于第一eFuse的电阻。 当感应电流被施加到eFuse时，识别出eFuses上产生的电压的差异，并用于指示可重新编程的eFuse是否处于编程状态或未编程状态。

公开(公告)号：US20070057697A1

公开(公告)日：2007-03-15

申请号：US11227026

申请日：2005-09-15

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R29/02

CPC分类号： G01R31/31708 ,  G01R31/31725

摘要： An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based on control inputs to the decoder. The synchronized output signals from the decoder are used as trigger signals to the plurality of flip-flops. The flip-flops sample the clock signals based upon the trigger signals and provide outputs to a logic gate. The logic gate operates on the outputs from the flip-flops to generate an output signal indicative of whether glitch-free operation is verified or is not verified.

公开(公告)号：US06404235B1

公开(公告)日：2002-06-11

申请号：US09651959

申请日：2000-08-31

申请人： Kevin J. Nowka ,  Hung Cai Ngo ,  Jieming Qi

发明人： Kevin J. Nowka ,  Hung Cai Ngo ,  Jieming Qi

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A dynamic circuit having reduced dynamic node switching latency. The operating status of the dynamic circuit alternates between a pre-charge phase in which a pre-charge device charges the dynamic node, and an evaluation phase in which data at the input of the dynamic circuit may or may not precipitate a dynamic node discharge. Each evaluation phase may be characterized as including an initial standby interval prior to the evaluation discharge, followed by an evaluate interval over which the dynamic node completes an evaluation discharge. A standby device is utilized to drive an output of the dynamic circuit low during a pre-charge phase and to maintain the output low during an standby interval in which dynamic circuit inputs do not result in the dynamic node being discharged. The dynamic circuit includes a standby control circuit that disables the standby device during the evaluation interval, resulting in reduced dynamic node switching capacitance. The dynamic circuit may further include a keeper device connected in parallel with the pre-charge device, wherein the keeper device maintains the dynamic node charged during the standby interval of an evaluation phase. A keeper control circuit responds to receipt of a control signal from the standby control circuit by disabling the keeper device during the evaluate interval such that switching latency is further reduced.

摘要翻译： 动态电路具有降低的动态节点切换等待时间。 动态电路的运行状态在预充电设备对动态节点充电的预充电阶段与动态电路输入端的数据可能或不会引起动态节点放电的评估阶段交替。 每个评价阶段可以被表征为包括在评估放电之前的初始待机间隔，随后是动态节点完成评估放电的评估间隔。 备用设备用于在预充电阶段期间将动态电路的输出驱动为低电平，并且在动态电路输入不导致动态节点放电的待机间隔期间将输出保持低电平。 动态电路包括备用控制电路，其在评估间隔期间禁用待机设备，导致动态节点开关电容减小。 动态电路还可以包括与预充电装置并联连接的保持器装置，其中保持器装置在评估阶段的待机间隔期间维持动态节点充电。 保持器控制电路通过在评估间隔期间禁用保持器装置来响应来自待机控制电路的控制信号的接收，从而进一步降低开关等待时间。

公开(公告)号：US08611368B2

公开(公告)日：2013-12-17

申请号：US13162917

申请日：2011-06-17

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/43 ,  H04L12/28

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

公开(公告)号：US08381143B2

公开(公告)日：2013-02-19

申请号：US13014828

申请日：2011-01-27

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F17/50

CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00221

摘要： A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

摘要翻译： 提供了一种用于占空比校正（DCC）电路的设计结构，其中已知DCC电路拓扑中的场效应晶体管（FET）中的对被替换为与DCC电路的开关耦合的线性电阻器，使得当开关断开时， 输入信号通过线性电阻器路由。 线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。 线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。 线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

公开(公告)号：US07786813B2

公开(公告)日：2010-08-31

申请号：US12098490

申请日：2008-04-07

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

IPC分类号： H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133

摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

公开(公告)号：US07782146B2

公开(公告)日：2010-08-24

申请号：US12098483

申请日：2008-04-07

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

IPC分类号： H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133

摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

摘要翻译： 公开了一种交错压控振荡器（VCO）。 VCO包括环形电路，其包括主逻辑反相器门的串联连接，与主逻辑反相器门的选定序列并联连接的多个延迟元件，至少一个温度补偿电路，包括与 一个或多个场效应晶体管，所述场效应晶体管响应于与温度成比例的补偿电压输入;以及电子电路，其与所述至少一个温度补偿电路进行信号通信，并且被配置为提供响应于温度的电压信号。 每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制，以及比例部分，包括用于调节通过至少一个逻辑反相器门的信号传输的控制。

公开(公告)号：US20090326862A1

公开(公告)日：2009-12-31

申请号：US12163081

申请日：2008-06-27

申请人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

发明人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

IPC分类号： G04F1/00 ,  H03L7/06

CPC分类号： H03K5/1565

摘要： Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.

摘要翻译： 本公开的实施例提供了用于时钟占空比测量的系统和方法。 时钟信号和时钟信号的补码在第一和第二预定定时窗口期间提供给电荷泵。 电荷泵可操作以分别在第一和第二定时窗口期间响应于时钟信号和时钟信号的补码产生第一和第二输出电压。 此外，预定的正电压和接地电压分别在预定的第三和第四定时窗口期间施加到电荷泵。 电荷泵可操作以分别在第三和第四定时窗口期间产生对应于预定正电压和接地电压的第三和第四输出电压信号。 然后，使用第一，第二，第三和第四电压来计算时钟的占空比。