Controlling user access to command execution

    公开(公告)号:US10397232B2

    公开(公告)日:2019-08-27

    申请号:US14750868

    申请日:2015-06-25

    摘要: Techniques are described for providing users with access to perform commands on network-accessible computing resources. In some situations, permissions are established for user(s) to execute command(s) on computing node(s) provided by an online service, such as by maintaining various permission information externally to those provided computing nodes for use in controlling users' ability to access, use, and/or modify the provided computing nodes. An interface component may use such external permissions information to determine if a particular user is authorized to execute one or more particular commands on one or more particular computing nodes, and to initiate simultaneous and independent execution of the command(s) on the computing node(s) when authorized. The interface component may further aggregate results from each computing node that executed the command(s), prior to providing the results to the user.

    Method and apparatus for repairing policies

    公开(公告)号:US10395200B2

    公开(公告)日:2019-08-27

    申请号:US15073104

    申请日:2016-03-17

    申请人: CA, Inc.

    摘要: A control computer implements a multi-stage process to automatically repair errors in a policy using selectable, pluggable repair modules. In the first stage, the control computer identifies the errors that caused the policies to fail the validation process, and associates the errors with corresponding repair modules. The repair modules comprise information that is needed to correct or repair the errors. In the second stage, the control computer generates commands for correcting the errors based on the information in the repair modules. In a third stage, the control computer applies the commands to the policies that failed the validation process to correct the errors.

    Generating a multi-column index for relational databases by interleaving data bits for selectivity

    公开(公告)号:US10394848B2

    公开(公告)日:2019-08-27

    申请号:US13953432

    申请日:2013-07-29

    IPC分类号: G06F16/22 G06F16/27 G06F16/28

    摘要: A multi-column index is generated based on an interleaving of data bits for selectivity for efficient processing of data in a relational database system. Two or more columns may be identified for inclusion in the multi-column index for a relational database table. Based, at least in part, on the interleaving of data bits for selectivity from the identified columns, a multi-column index is generated for the relational database table that provides a respective index value for each entry in the relational database table. The entries of the relational database table may then be stored according to the index values of the multi-column index.

    Transmit-receive switch
    47.
    发明授权

    公开(公告)号:US10389358B1

    公开(公告)日:2019-08-20

    申请号:US16125133

    申请日:2018-09-07

    申请人: Apple Inc.

    IPC分类号: H04B1/44 H03K19/0185 H04B1/48

    摘要: A transmit-receive (T/R) switch is disclosed. An apparatus including a T/R switch includes a transceiver to transmit signals to an antenna and to receive signals from the antenna. The signals are conveyed to and from the transceiver by a T/R switch. The T/R switch includes a transmit path and a receive path. The receive path includes a three-port inductor having a first terminal coupled to an input/output (I/O) terminal of the T/R switch and a second terminal coupled to a first pass transistor, and a third terminal. A pull-down transistor is coupled between the third terminal and a ground node. When active, the pull-down transistor pulls the receive path down toward ground.

    Clock pulse generation circuit
    48.
    发明授权

    公开(公告)号:US10389335B1

    公开(公告)日:2019-08-20

    申请号:US15970986

    申请日:2018-05-04

    申请人: Apple Inc.

    摘要: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.

    System and method for conditionally updating an item with attribute granularity

    公开(公告)号:US10387402B2

    公开(公告)日:2019-08-20

    申请号:US15362484

    申请日:2016-11-28

    IPC分类号: G06F16/23 G06F16/27

    摘要: A system that implements a scaleable data storage service may maintain tables in a non-relational data store on behalf of clients. Each table may include multiple items. Each item may include one or more attributes, each containing a name-value pair. Attribute values may be scalars or sets of numbers or strings. The system may provide an API usable to request that values of one or more of an item's attributes be updated. An update request may be conditional on expected values of one or more item attributes (e.g., the same or different item attributes). In response to a request to update the values of one or more item attributes, the previous values and/or updated values may be optionally returned for the updated item attributes or for all attributes of an item targeted by an update request. Items stored in tables may be indexed using a simple or composite primary key.

    Operating on data streams using chained hardware instructions

    公开(公告)号:US10387163B2

    公开(公告)日:2019-08-20

    申请号:US15841375

    申请日:2017-12-14

    发明人: Jonathan Helman

    IPC分类号: G06F9/30 G06F9/38 G06F9/54

    摘要: A method for accessing and using a hardware acceleration circuit in a computer system is disclosed. The computer system may receive a single call to a particular library function that is implemented by a hardware acceleration circuit included in the computer system. A plurality of chained hardware instructions is generated in response to the single call, wherein the plurality of chained hardware instructions is based on different ones of a plurality of flags and a plurality of data streams specified by the single call. The computer system may send the plurality of chained hardware instructions to the hardware acceleration circuit for execution.