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公开(公告)号：US10381275B2
公开(公告)日：2019-08-13
申请号：US15749444
申请日：2018-01-02
Inventor： Guanghui Hong , Qiang Gong
IPC: H01L21/66 , H01L27/12 , H01L21/768 , H01L21/48 , G02F1/13
Abstract: The present invention provides an array substrate and an repairing method thereof, wherein the array substrate includes adjacent two level GOA unit circuits, wherein an output terminal of a Nth level GOA unit circuit is connected to a Nth level gate line, an output terminal of a N+1th level GOA unit circuit is connected to a N+1th level gate line; and a repairing structure disposed between the Nth level gate line and the N+1th level gate line, the repairing structure configured to turn on the Nth level gate line and the N+1th level gate line by melting when the Nth level GOA unit circuit or the N+1th level GOA unit circuit damaged. A repairing structure is added between two adjacent gate lines, when a certain GOA unit circuit is damaged, the repairing structure is melted by a laser to make the adjacent two gate lines communicate with each other.
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公开(公告)号：US10379397B1
公开(公告)日：2019-08-13
申请号：US16300048
申请日：2018-09-22
Inventor： Yuejun Tang
IPC: H01L27/32 , G02F1/1335 , G02F1/1343 , H01L51/52 , G02F1/1368 , H01L27/12
Abstract: The present invention teaches a design method and a structure for improving display quality of an irregular shaped panel. The design method includes: disposing an initial shading layer along an edge of the panel's actual display area; for a pixel not entirely covered by the initial shading layer but having at least a sub-pixel entirely covered by the initial shading layer, setting the pixel to be turned off at all times, or extending the initial shading layer to cover the pixel; and, for a pixel and each of its sub-pixels not entirely covered by the initial shading layer, setting the pixel so that a brightness ratio among its sub-pixels is, under a same driving condition, identical or close to that among the sub-pixels of a normal pixel. The design method and structure reduce or eliminate jagged feel and color shift along an edge of the area of notch or irregularity.
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公开(公告)号：US20190244982A1
公开(公告)日：2019-08-08
申请号：US16147880
申请日：2018-10-01
Inventor： Gaiping Lu , Jiawei Zhang , Wei Tang
IPC: H01L27/12 , H01L29/786 , G02F1/1362 , G02F1/1343 , H01L21/768 , G02F1/1368 , G02F1/1333 , H01L29/66
CPC classification number: H01L27/1244 , G02F1/13338 , G02F1/13439 , G02F1/136204 , G02F1/136227 , G02F1/1368 , G02F2001/13685 , G02F2202/104 , G06F3/041 , G06F2203/04103 , H01L21/76802 , H01L21/76834 , H01L21/76877 , H01L27/1248 , H01L27/1262 , H01L29/66757 , H01L29/78603 , H01L29/78636 , H01L29/78675
Abstract: The present disclosure provides a thin film transistor (TFT) substrate and a manufacturing method thereof. The TFT substrate include a TFT; a flat layer to cover the TFT; an opening hole defined in the flat layer and corresponding to a drain of the TFT; a bottom of the opening hole to retain a part of the flat layer for forming a flat layer sheet; a first metal layer formed on the flat layer; a first insulating layer formed on the first metal; a second metal formed on the first insulating layer and pass through the flat layer sheet for electrically connecting to the drain.
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公开(公告)号：US10371992B2
公开(公告)日：2019-08-06
申请号：US14897346
申请日：2015-08-14
Inventor： Yuejun Tang
IPC: G02F1/1343 , G02F1/1337 , C09K19/02 , G02F1/137
Abstract: A blue phase liquid crystal panel is disclosed, which includes an upper substrate, a lower substrate, and blue phase liquid crystal that is arranged between the upper substrate and the lower substrate. The upper substrate is provided with a first electrode base layer which has a plurality of first protrusions, and the lower substrate is provided with a second electrode base layer which has a plurality of second protrusions. The first protrusions each extend to a position between two adjacent second protrusions, and the second protrusions each extend to a position between two adjacent first protrusions. The first protrusion is provided with a common electrode, and the second protrusion is provided with a pixel electrode. The driving voltage of blue phase liquid crystal in the panel can be reduced.
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公开(公告)号：US10367010B2
公开(公告)日：2019-07-30
申请号：US16003752
申请日：2018-06-08
Inventor： Li Wang
IPC: H01L27/12 , H01L23/528 , G02F1/1368 , H01L29/786 , G02F1/1362
Abstract: An display device is provided which including a stacked array substrate, a display medium layer and an opposite substrate. The array substrate includes a substrate, and plurality of arrayed thin film transistors and conductor layers disposed on the substrate, the conductor layers have a plurality of gate signal lines for transmitting gate signals, each of the gate signal lines extends along a first direction and connects to the plurality of the thin film transistors disposed along the first direction, resistances of the gate signal lines are decreased along a transmitting direction of the gate signals. It realizes that the actual driving voltages of the gate signal line in respective regions are consistent with the ideal driving voltage by designing a gate signal line with a uniform decrease of resistance in a transmitting direction of the gate signal.
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Patent Agency Ranking
406.发明授权公开(公告)号：US10366911B2
公开(公告)日：2019-07-30
申请号：US15504330
申请日：2016-12-26
Inventor： Fan Tang
IPC: H01L21/683 , C23C14/04 , H01L51/56 , B32B27/08 , B32B27/30 , B32B7/12 , H01L21/50 , H01L51/00 , C23C14/24
Abstract: A carrier substrate for carrying an OLED in manufacturing process is disclosed. The carrier substrate includes a substrate and an attracted layer disposed on a surface of the substrate, wherein the attracted layer includes a resin layer and multiple magnetic nanoparticles distributed in the resin layer. A manufacturing method for the same is also disclosed. When manufacturing an OLED, the attracted layer receives the attraction force provided by the attraction body so that the deformation of the substrate for carrying an OLED in manufacturing generating by drooping because of gravity force can be canceled out or decreased in order to avoid a shadow effect and a color mixing.
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公开(公告)号：US10360850B2
公开(公告)日：2019-07-23
申请号：US15544013
申请日：2017-04-27
Inventor： Weinan Yan , Fu-Chih Chang
IPC: G09G3/32 , G09G3/3233
Abstract: Disclosed is a display module driving device, comprising a display driving module, driving each of the organic light emitting diodes to emit light; a plurality of light sensors, detecting brightnesses of corresponding light sensors and outputting corresponding actual brightness values; a gray scale brightness conversion module, acquiring a gray scale value of each of the sub pixels in a present display frame and converting the gray scale value into a corresponding target brightness value; a comparing module, receiving and comparing the target brightness value and the corresponding actual brightness value of each of the sub pixels; and a controlling module, controlling the display driving module to drive the organic light emitting diodes to maintain the target brightness value as the actual brightness value is equal to the target brightness value. The display module driving device can effectively solve the problem of the display difference caused by the uneven brightness.
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公开(公告)号：US20190221672A1
公开(公告)日：2019-07-18
申请号：US15575107
申请日：2017-08-21
Inventor： Donghui Xiao
IPC: H01L29/786 , H01L29/51 , H01L29/66 , H01L21/02 , H01L21/28 , H01L21/265
Abstract: The present invention discloses a preparation method of a low temperature polysilicon thin film transistor including: successively forming a polysilicon active layer and a gate insulating layer covering the active layer on a base substrate; implanting nitrogen ions on a surface of the polysilicon active layer facing the gate insulating layer by an ion implantation process to form an ion implantation layer; and recrystallizing the ion implantation layer by a high temperature annealing process to form a silicon nitride spacing layer between the polysilicon active layer and the gate insulating layer. The present invention also provides a low temperature polysilicon thin film transistor including a polysilicon active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode successively provided on a base substrate, wherein a connection interface between the polysilicon active layer and the gate insulating layer is formed with a silicon nitride spacing layer, and the silicon nitride spacing layer and the polysilicon active layer are in a integrally interconnected structure.
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409.发明授权公开(公告)号：US10355034B2
公开(公告)日：2019-07-16
申请号：US15578562
申请日：2017-10-13
Inventor： Tao Wang
IPC: H01L27/12 , H01L21/3213 , H01L21/02 , H01L21/285 , H01L29/66 , H01L29/786
Abstract: The present disclosure provides a low-temperature polycrystalline silicon array substrate which includes a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polycrystalline silicon active layer disposed on the buffer layer, the groove is located at a channel of a thin film transistor, and the buffer layer covers the groove to form an air layer in the groove. The present disclosure further provides a manufacturing method of a low-temperature polycrystalline silicon array substrate, mainly including: manufacturing a groove at a channel of a thin film transistor on a substrate; depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the groove through an etching process; sequentially forming a buffer layer and an amorphous silicon layer on the substrate; and removing the metal sacrificial layer in the groove to form an air layer in the groove.
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公开(公告)号：US10353261B2
公开(公告)日：2019-07-16
申请号：US15561062
申请日：2017-09-21
Inventor： Zhenzhou Xing
IPC: H01L27/12 , G02F1/1368 , G02F1/1343 , G02F1/1362 , H01L29/786
Abstract: The present application discloses a RGBW liquid crystal panel includes a plurality of scanning lines and a plurality of data lines, and a plurality of sub-pixel regions formed by the division of the plurality of scanning lines and the plurality of data lines; each sub-pixel region includes a sub-pixel and a thin film transistor, a gate electrode and a source electrode of each thin film transistor are connected to a scanning line and a data line, respectively, a drain electrode of each thin film transistor is connected to the sub-pixel; wherein, the plurality of sub-pixels includes a plurality of first white sub-pixels and a plurality of second white sub-pixels, the thin film transistor corresponding to the first white sub-pixel and the thin film transistor corresponding to second white sub-pixel have different channel width-length ratio, so that the first white sub-pixel and the second white sub-pixel have different luminance.
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