公开(公告)号：US20110025381A1

公开(公告)日：2011-02-03

申请号：US12902904

申请日：2010-10-12

申请人： Seiji YAMAHIRA

发明人： Seiji YAMAHIRA

IPC分类号： H03K21/00 ,  H03B19/00 ,  H03B19/06

CPC分类号： G06F1/06 ,  H03K5/135 ,  H03K5/15013 ,  H03K23/425

摘要： A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal.

摘要翻译： 用于分割多相时钟信号的频率的分频电路，即使多相时钟信号具有高频率也能够确保足够的数据锁存时间，包括主锁存电路，其产生反相数据信号，用于 例如，八相时钟信号的八个时钟信号中的两个，以及使用八个时钟信号作为触发来接收反相数据信号作为公共数据信号的子锁存电路。

公开(公告)号：US07839187B2

公开(公告)日：2010-11-23

申请号：US12418714

申请日：2009-04-06

申请人： Chow-Peng Lee ,  Aung Aung Yinn

发明人： Chow-Peng Lee ,  Aung Aung Yinn

IPC分类号： H03B19/06

CPC分类号： H03K23/667 ,  H03K23/68

摘要： A frequency divider includes a transmission gate, a first inverter, a first switch circuit, a second switch circuit, and a second inverter. The transmission gate transmits a clock signal according to an inverted enable signal. The first inverter inverts the clock signal outputted from the transmission gate. The first switch circuit generates a first control signal according to the inverted clock signal and an output signal of the frequency divider. The second switch circuit generates a second control signal according to the clock signal, the inverted clock signal, and the first control signal. The second inverter inverts the second control signal to generate the output signal. The frequency of the clock signal is a multiple of the frequency of the output signal.

摘要翻译： 分频器包括传输门，第一反相器，第一开关电路，第二开关电路和第二反相器。 发送门根据反相使能信号发送时钟信号。 第一个反相器反转从传输门输出的时钟信号。 第一开关电路根据反相时钟信号和分频器的输出信号产生第一控制信号。 第二开关电路根据时钟信号，反相时钟信号和第一控制信号产生第二控制信号。 第二反相器反转第二控制信号以产生输出信号。 时钟信号的频率是输出信号频率的倍数。

公开(公告)号：US20100253398A1

公开(公告)日：2010-10-07

申请号：US12417676

申请日：2009-04-03

申请人： Utku Seckin

发明人： Utku Seckin

IPC分类号： H03B19/06

CPC分类号： H03K23/68 ,  H03K23/667

摘要： A fully differential frequency divider includes a first fully differential single-stage latch circuit configured to receive an input signal and provide a corresponding output signal upon transition of a clock signal, the output signal corresponding to an in-phase portion of a communication signal, and a second fully differential single-stage latch circuit coupled to the first fully differential single-stage latch circuit, the second fully differential single-stage latch circuit configured to provide a corresponding output signal upon transition of the clock signal. The second fully differential single-stage latch circuit is also configured to receive as an input signal the output signal of the first fully differential single-stage latch circuit, the output signal of the second fully differential single-stage latch circuit corresponding to a quadrature-phase portion of the communication signal, where the output signal of the second fully differential single-stage latch circuit is provided as the input signal to the first fully differential single-stage latch circuit.

摘要翻译： 完全差分分频器包括：第一全差分单级锁存电路，被配置为接收输入信号，并且在时钟信号转换时提供对应的输出信号，对应于通信信号的同相部分的输出信号，以及 第二全差分单级锁存电路，耦合到第一全差分单级锁存电路，第二全差分单级锁存电路被配置为在时钟信号转变时提供对应的输出信号。 第二全差分单级锁存电路还被配置为接收作为输入信号的第一全差分单级锁存电路的输出信号，第二全差分单级锁存电路的输出信号对应于正交 - 通信信号的相位部分，其中第二全差分单级锁存电路的输出信号作为输入信号被提供给第一全差分单级锁存电路。

公开(公告)号：US20100164562A1

公开(公告)日：2010-07-01

申请号：US12391263

申请日：2009-02-24

申请人： Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

发明人： Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

IPC分类号： H03B19/06 ,  H03B19/00 ,  H03K3/017 ,  H03L7/06

CPC分类号： H03L7/1976 ,  G06F1/08 ,  H03K23/68

摘要： A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.

摘要翻译： 示出了时钟发生器。 上述时钟发生器包括多模式分频器和Δ-Σ调制器。 多模式分频器通过切换其相位进行归档。 多模分频器有效地增加了时钟发生器的工作频率，并且具有半周期分辨率的特性，用于在其频谱扩展时减少输出时钟信号的抖动。 此外，Δ-Σ调制器通过在其中添加几个分量来增加三角形调制的精度并减少量化误差。 因此，时钟发生器可以扩展到可编程时钟发生器。

公开(公告)号：US20080265934A1

公开(公告)日：2008-10-30

申请号：US12081771

申请日：2008-04-21

申请人： Hayato Ogawa

发明人： Hayato Ogawa

IPC分类号： H03K19/00 ,  H03L7/06 ,  H03B19/06

CPC分类号： H03B19/06 ,  G01R31/31727 ,  H03L7/07 ,  H03L7/23

摘要： A semiconductor integrated circuit includes S PLLs (S is an integer satisfying S≧2), and the (k−1)th PLL 12(k-1) (k is an integer satisfying 2≦k≦S) is connected to the kth PLL 12k in the test mode. In this manner, the examination of S PLLs can be performed in a single test, and thereby it can reduce the time needed to examine PLLs for the in semiconductor integrated circuit having a plurality of PLLs.

摘要翻译： 半导体集成电路包括S个PLL（S是满足S> = 2的整数），第（k-1）个PLL 12（k-1）（k是满足2 <= k <= S）在测试模式下连接到第k个PLL 12＆lt; k＆gt;。 以这种方式，可以在单个测试中执行S PLL的检查，从而可以减少检查具有多个PLL的半导体集成电路中的PLL所需的时间。

公开(公告)号：US06867656B2

公开(公告)日：2005-03-15

申请号：US10463264

申请日：2003-06-17

申请人： Seyed-Ali Hajimiri ,  Hui Wu

发明人： Seyed-Ali Hajimiri ,  Hui Wu

IPC分类号： H03B5/12 ,  H03B27/00 ,  H03L7/24 ,  H03B19/06

CPC分类号： H03L7/24 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B27/00

摘要： A system for generating in-phase and quadrature phase signals is provided. The system includes a first and a second differential output, such as from a sinusoidal oscillator. A first injection-locked frequency divider, such as one that uses an LC oscillator in conjunction with cross-coupled transistors, receives the first differential output and generates a in-phase or in-phase output. A second injection-locked frequency divider receives the second differential output and generates a quadrature phase output.

摘要翻译： 提供了一种用于产生同相和正交相位信号的系统。 该系统包括第一和第二差分输出，例如来自正弦振荡器。 第一注入锁定分频器，例如使用LC振荡器与交叉耦合晶体管结合的分频器，接收第一差分输出并产生同相或同相输出。 第二注入锁定分频器接收第二差分输出并产生正交相位输出。

公开(公告)号：US4931921A

公开(公告)日：1990-06-05

申请号：US358330

申请日：1989-05-30

申请人： Dale R. Anderson

发明人： Dale R. Anderson

IPC分类号： H03B19/06

CPC分类号： H03B19/06

摘要： A single-transistor frequency doubler uses an elliptical filter on the collector of the transistor to improve the bandwidth of the doubler. Bandwidths in excess of thirty five percent having relatively constant output power levels at frequencies over 200 MHz can be realized.

摘要翻译： 单晶体管倍频器在晶体管的集电极上使用椭圆滤波器来改善倍频器的带宽。 可以实现在超过200MHz的频率具有相对恒定的输出功率电平的带宽超过百分之三十五。

公开(公告)号：US4359688A

公开(公告)日：1982-11-16

申请号：US202166

申请日：1980-10-30

申请人： George D. Haville

发明人： George D. Haville

IPC分类号： G06G7/22 ,  H03B19/00 ,  H03B19/06

CPC分类号： G06G7/22 ,  H03B19/00

摘要： A frequency multiplying circuit for producing double frequency sine and cosine output signals sin 2x and cos 2x from sine and cosine input signals sin x and cos x, comprising two multiplier circuits, each having an output e.sub.0 and four inputs a.sub.1, a.sub.2, b.sub.1 and b.sub.2 and being adapted to perform multiplication in accordance with the following relation:e.sub.0 =K(a.sub.1 -a.sub.2)(b.sub.1 -b.sub.2);sine and cosine input amplifiers for supplying the sin x and cos x input signals; means for supplying the cos x input signal to the a.sub.1 input of the first multiplier circuit; means for supplying the cos x signal to the b.sub.1 input of the first multiplier circuit, means affording a gain of 2 in the first channel, relative to the second channel, means for supplying zero input to the a.sub.2 and b.sub.2 inputs of the first multiplier circuit; means for supplying the cos x input signal to the a.sub.1 and b.sub.1 inputs of the second multiplier circuit; a phase inverter for supplying a negative sin x input to the a.sub.2 input of the second multiplier circuit; and means for supplying the sin x input signal to the b.sub.2 input of the second multiplier circuit, whereby the first and second multiplier circuits develop output signals proportional to sin 2x and cos 2x, respectively.

摘要翻译： 一种用于从正弦和余弦输入信号sin x和cos x产生双频正弦和余弦输出信号sin 2x和cos 2x的倍频电路，包括两个乘法器电路，每个具有输出e0和四个输入a1，a2，b1和b2 并适应于根据以下关系进行乘法：e0 = K（a1-a2）（b1-b2）; 正弦和余弦输入放大器，用于提供sin x和cos x输入信号; 用于将cos x输入信号提供给第一乘法电路的a1输入的装置; 用于将cos x信号提供给第一乘法器电路的b1输入的装置，相对于第二通道在第一通道中提供2的增益的装置，用于向第一乘法电路的a2和b2输入端提供零输入的装置 ; 用于将cos x输入信号提供给第二乘法电路的a1和b1输入的装置; 用于向第二乘法电路的a2输入端输入负的负x sinx的相位逆变器; 以及用于将sin x输入信号提供给第二乘法电路的b2输入的装置，由此第一和第二乘法器电路分别产生与sin 2 x和cos 2 x成比例的输出信号。

公开(公告)号：US12087867B2

公开(公告)日：2024-09-10

申请号：US17093305

申请日：2020-11-09

申请人： California Institute of Technology

发明人： Jose Vicente Siles Perez ,  Choonsup Lee ,  Robert H. Lin ,  Alejandro Peralta

IPC分类号： H01L29/872 ,  H01L23/66 ,  H03B19/06

CPC分类号： H01L29/872 ,  H01L23/66 ,  H03B19/06 ,  H01L2223/6627 ,  H01L2223/6688

摘要： A solid-state device chip including diodes (generating a higher or lower frequency output through frequency multiplication or mixing of the input frequency) and a novel on-chip diplexing design that allows combination of two or more multiplier or mixer structures operating at different frequency bands within the 50-5000 GHz range within a same chip and/or waveguide. The on-chip diplexing design consists of a single-substrate multiplier chip with two or more multiplying structures each one containing 2 or more Schottky diodes. The diodes in each structure are tuned to one portion of the target frequency band, resulting in the two or more structures working together as a whole as a large broadband multiplier or mixer. Thus, an increase in bandwidth from 10-15% (current state-of-the-art) to at least 40% is achieved. Depending on the target frequencies, each subset of diodes within the chip can be designed to work either as a doubler or a tripler.

公开(公告)号：US10651833B2

公开(公告)日：2020-05-12

申请号：US16062777

申请日：2015-12-31

申请人： SHANGHAI INSTITUTE OF CERAMICS, CHINESE ACADEMY OF SCIENCES ,  R&D CENTER, SHANGHAI INSTITUTE OF CERAMICS

发明人： Wei Huang ,  Erwei Shi

IPC分类号： H03B19/06 ,  H03K5/04 ,  H03K17/78

摘要： A controllable splitting method comprises: electrically connecting a photoconductive switch between input and output ends of a current pulse; connecting a time domain signal of the input current pulse to an external triggering port of a pulse laser; emitting a laser pulse to irradiate the switch; when no current pulse is input, failing to receive an external triggering signal and not outputting the laser pulse, the switch being in an off state without the irradiation of the laser pulse, and no current being output; when the current pulse is input, triggering the pulse laser to synchronously output the laser pulse on a time domain, irradiating the switch so that the switch is in an on state and the current pulse is output; and forming, at the output end, a current pulse signal synchronous with a time domain of the input end and having a split waveform.