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公开(公告)号：US5298899A
公开(公告)日：1994-03-29
申请号：US899856
申请日：1992-06-17
申请人： Kwang-Sok Oh , Geun-Rae Cho , Jae-Bum Hong
发明人： Kwang-Sok Oh , Geun-Rae Cho , Jae-Bum Hong
CPC分类号： H03M3/042 , H03M7/3002
摘要： A separator provides peak value data and distance value data, a pair of registers respectively store multiple peak values and distance value data between peak values, a subsequent stage subtracts the series of multiple successive peak values to provide difference data, and divides the difference data by the distance value data to provide quotient data representative of a step size, and an interpolator provides a reproduced waveform by interpolating the peak value data and the quotient data.
摘要翻译： 分离器提供峰值数据和距离值数据，一对寄存器分别在峰值之间存储多个峰值和距离值数据，后续级减去多个连续峰值序列以提供差分数据，并将差分数据除以 所述距离值数据提供表示步长的商数据，并且内插器通过内插所述峰值数据和商数据来提供再现波形。
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公开(公告)号：US5289549A
公开(公告)日：1994-02-22
申请号：US71947
申请日：1993-06-04
CPC分类号： H04N19/124 , H03M3/042 , H04N19/50 , H04N19/593
摘要： An apparatus for processing a stream of digital data to provide a set of linear prediction coefficients and prediction error sequence representing said block of data which, when used to reconstruct the block of data, will reconstruct the data with a minimum distortion level is described.
摘要翻译： 一种用于处理数字数据流以提供一组线性预测系数的装置和表示所述数据块的预测误差序列，当用于重建数据块时，将以最小失真水平重建数据。
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33.发明授权Circuit for PCM conversion of an analog signal, with improvement in gain-tracking 失效模拟信号的PCM转换电路，具有增益跟踪的改进
公开(公告)号：US5287106A
公开(公告)日：1994-02-15
申请号：US187507
申请日：1988-04-28
CPC分类号： H03M1/0604 , H03M1/12
摘要： The circuit includes a filter to which an analog signal is applied, a quantizer driven by the filter, a sampler at a desired frequency driven by the quantizer and a PCM encoder driven by the sampler. The quantizer generates a quantize signal according to the received analog signal and further generates a difference signal according to the difference between a quantized signal and the analog signal. A feedback circuit feeds back the difference signal from the quantizer to a stage of the filter so that the overall transfer function from the input of the feedback circuit to the output of the filter is equivalent to a low pass filtering.
摘要翻译： 电路包括施加模拟信号的滤波器，由滤波器驱动的量化器，由量化器驱动的期望频率的采样器和由采样器驱动的PCM编码器。 量化器根据接收到的模拟信号生成量化信号，并根据量化信号和模拟信号之间的差产生差分信号。 反馈电路将差分信号从量化器反馈到滤波器的级，使得从反馈电路的输入到滤波器的输出的整体传递函数等效于低通滤波。
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34.发明授权
公开(公告)号：US5257026A
公开(公告)日：1993-10-26
申请号：US870270
申请日：1992-04-17
摘要： A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta. coefficient is stored in a block (16) and is generated during a calibration cycle by a .delta. processor (39). The .delta. processor (39) receives the output of the compensation circuit (14) and the digital output from the summing junction (36) when the calibration multiplexer (10) sets the input to zero. A control circuit (40) controls the overall operation, with the calibration operation initiated in response to either an external signal on a line (30) or an internally generated signal. After calibration, the value of the .delta. coefficient is frozen and the calibration multiplexer (10) selects the analog input.
摘要翻译： 用于校准多电平Δ-Σ调制器（12）中的非线性的校准方法和装置包括在输入端上的校准多路复用器（10），用于在校准模式中选择用于输入到Δ-Σ调制器的零电压 （12）。 Δ-Σ调制器（12）具有三个电平，即+1,0，-1，向处理器（32）输入的+1电平，以及输入到处理器（34）的-1电平。 处理器（34）的输出被输入到补偿电路（14），该补偿电路将由-1处理器（34）产生的值偏移系数增量。 然后，补偿电路（14）的输出被输入到也接收处理器（32）的输出的求和结（36）的负输入，提供数字输出的求和结（36）的输出。 处理器（32）和（34）通过单独的累加器来实现，所述累加器在相关的滤波器系数和地之间切换存储在ROM（35）中的滤波器系数。 增量系数存储在块（16）中，并且在校准周期期间由增量处理器（39）产生。 当校准多路复用器（10）将输入设置为零时，Δ处理器（39）接收补偿电路（14）的输出和来自求和结（36）的数字输出。 控制电路（40）控制总体操作，其中响应于线路（30）上的外部信号或内部产生的信号启动校准操作。 校准后，delta系数的值被冻结，校准多路复用器（10）选择模拟输入。
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公开(公告)号：US5245345A
公开(公告)日：1993-09-14
申请号：US777754
申请日：1991-10-11
申请人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatuya Kishii , Kuniaki Morita , Juhro Hoshi
发明人： Takayuki Kohdaka , Mituhiro Homme , Masamitu Hirano , Tatuya Kishii , Kuniaki Morita , Juhro Hoshi
摘要： The digital-to-analog conversion apparatus operates in synchronization with a system clock signal having a short period to oversample and delta-sigma-modulate a digital input to produce a requantized digital signal. The system clock signal is mixed with noise leaked back due to the oversampling and delta-sigma modulating operation. The system clock signal is frequency-divided by the rate of one-fourth or less to produce a divided clock signal having a long period and being free of the noise. The requantized digital signal is detected each long period, and is pulse-modulated according to the detected results to generate a pulse signal having the long period. This pulse signal is low-pass-filtered to produce an analog output having improved S/N ratio.
摘要翻译： 数模转换装置与具有短周期的系统时钟信号同步地进行过采样，并对数字输入进行Δ-Σ调制以产生再量化的数字信号。 系统时钟信号与由于过采样和Δ-Σ调制操作而被泄漏的噪声混合。 系统时钟信号被四分之一或更小的速率分频，以产生具有较长周期并且没有噪声的分频时钟信号。 每隔长时间检测重新量化的数字信号，并根据检测结果进行脉冲调制，生成长周期的脉冲信号。 该脉冲信号被低通滤波以产生具有改善的S / N比的模拟输出。
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36.发明授权Digital-to-analog converting device using decoders and parallel-to-serial converters 失效使用解码器和并行到串行转换器的数模转换器件
公开(公告)号：US5243346A
公开(公告)日：1993-09-07
申请号：US810678
申请日：1991-12-19
申请人： Daijiro Inami
发明人： Daijiro Inami
CPC分类号： H03M1/662
摘要： In a digital-to-analog converting device for converting an input digital signal into an output analog signal, a converting circuit converts the input digital signal into a first and a second digital signal which are alternatingly produced in parallel in response to clock pulses. A first and a second decoder are for decoding the first and the second digital signals into a first and a second decoded parallel digital signal. A first and a second parallel-serial converter are for converting the first and the second decoded parallel digital signals into a first and a second serial digital signal in response to an oversampling clock pulses. A first and a second digital-to-analog converter are for converting the first and the second serial digital signals into a first and a second analog signal. An analog adder adds the first and the second analog signals into a sum analog signal. An analog integrator is for integrating the sum analog signal into the output analog signal.
摘要翻译： 在用于将输入数字信号转换为输出模拟信号的数模转换装置中，转换电路将输入的数字信号转换成响应于时钟脉冲并行交替产生的第一和第二数字信号。 第一和第二解码器用于将第一和第二数字信号解码为第一和第二解码并行数字信号。 第一和第二并行 - 串行转换器用于响应于过采样时钟脉冲将第一和第二解码并行数字信号转换为第一和第二串行数字信号。 第一和第二数模转换器用于将第一和第二串行数字信号转换为第一和第二模拟信号。 模拟加法器将第一和第二模拟信号加到和模拟信号中。 模拟积分器用于将总和模拟信号整合到输出模拟信号中。
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37.发明授权Adaptive predictive coding encoder for compression of quantized digital audio signals 失效用于压缩数字音频信号的自适应预编码编码器
公开(公告)号：US5166981A
公开(公告)日：1992-11-24
申请号：US524088
申请日：1990-05-16
申请人： Naoto Iwahashi , Kenzo Akagiri
发明人： Naoto Iwahashi , Kenzo Akagiri
CPC分类号： H04B14/046 , H03M7/3004
摘要： In an adaptive predictive coding (APC) encoder for compression of quantized digital audio, the signal-to-quantization noise ratio is improved and more complicated input signal spectra can be processed through use of an input signal frequency spectrum detector employing linear predictive coding (LPC) analysis for setting the coefficients of the requantization error noise filter. The detector operates in synchronism with the predictive and noise filters so as to minimize the number of processing calculations while maximizing processing speed.
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公开(公告)号：US5153593A
公开(公告)日：1992-10-06
申请号：US514990
申请日：1990-04-26
摘要： A precision sigma-delta A/D converter having a desired number of cascaded stages is disclosed herein. The multi-stage sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal X(z) to an output sequence of digital words. The converter (10) of the present invention includes a first sigma-delta converter stage (14) for generating a first sequence of digital words and a quantization error signal in response to the analog input signal X(z). An interstage amplifier (34) then amplifies the quantization error signal by a first gain factor G. The present invention further includes a second sigma-delta converter stage (18) for generating a second sequence of digital words in response to the amplified quantization error signal. The first and second sequences are next filtered by a digital noise cancellation network (31, 32) and the filtered second sequence is divided by the first gain factor G via a divider circuit (38). A summing circuit (40) provides the output sequence of digital words by summing the filtered first sequence and the divided second sequence. The digital noise cancellation network (32) is also used to compensate for errors due to analog component imperfections, e.g., capacitor mismatches and finite operational amplifier gain.
摘要翻译： 本文公开了具有期望数量的级联级的精度Σ-ΔA/ D转换器。 本发明的多级Σ-Δ模数转换器（10）可操作以将模拟输入信号X（z）转换为数字字的输出序列。 本发明的转换器（10）包括用于响应于模拟输入信号X（z）产生数字字的第一序列和量化误差信号的第一Σ-Δ转换器级（14）。 级间放大器（34）然后通过第一增益因子G放大量化误差信号。本发明还包括第二Σ-Δ转换器级（18），用于响应于放大的量化误差信号产生第二数字字序列 。 第一和第二序列接下来被数字噪声消除网络（31,32）滤波，并且滤波的第二序列经由除法电路（38）被第一增益因子G除。 求和电路（40）通过对经滤波的第一序列和分割的第二序列相加来提供数字字的输出序列。 数字噪声消除网络（32）还用于补偿由于模拟部件缺陷引起的误差，例如电容器失配和有限运算放大器增益。
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公开(公告)号：US5107519A
公开(公告)日：1992-04-21
申请号：US429056
申请日：1989-10-30
申请人： Hisashi Ishikawa
发明人： Hisashi Ishikawa
IPC分类号： H03M3/04
CPC分类号： H03M7/3044 , H04N19/126 , H04N19/50
摘要： A coding device comprises a coding circuit in which a range of values, which local decoded values are permitted to have is made narrower than a range of values, which input sample values are permitted to have when coding a differential value between an input sample value and its predictive value. A decoding device substitutes a decoded value to be subsequently decoded for a decoded value in which a gradient overload is produced when decoding a code provided by coding a differential value between an input sample value and its predictive value.
摘要翻译： 一种编码装置，包括：编码电路，其中允许局部解码值的值的范围比值的范围窄，当输入样本值和 其预测价值。 解码装置将解码后的值替换为解码通过编码输入样本值与其预测值之间的差分值而提供的代码时产生梯度过载的解码值。
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公开(公告)号：US5068661A
公开(公告)日：1991-11-26
申请号：US244047
申请日：1988-09-13
申请人： Tetsuhiko Kaneaki , Kozo Nuriya , Yasunori Tani
发明人： Tetsuhiko Kaneaki , Kozo Nuriya , Yasunori Tani
CPC分类号： H03M3/418
摘要： A noise shaping quantization D/A converter in which an input digital signal is supplied to a single-integration sigma delta modulation circuit having quantization levels which include zero level, with a quantization error signal from the single-integration circuit being supplied to a double-integration noise shaping quantization circuit having quantization levels which also include zero level, and an output signal from the double-integration circuit being differentiated and summed with the single-integration circuit output to obtain a bit-compressed digital signal for D/A conversion. Offset of the analog output signal during a zero hold status of the input digital signal is eliminated, and increased efficiency of supply voltage utilization is attained, together with increased S/N ratio.
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