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1.发明授权Resampler for a bit pump and method of resampling a signal associated therewith 有权用于位泵的重采样器和与其相关联的信号重采样的方法公开(公告)号：US07542536B2
公开(公告)日：2009-06-02
申请号：US11234361
申请日：2005-09-23
IPC分类号： H03K1/00
CPC分类号： H04L7/0029 , H04B3/23 , H04L25/03057 , H04L25/03343 , H04L27/2626 , H04L27/2647 , H04L2025/03414
摘要： A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that receives the plurality of intermediate samples via one delay line of single bits and select one thereof, thereby providing an output sample that corresponds to a phase of the oscillator.
摘要翻译： 重采样器，对信号进行重采样的方法以及使用该信号的位泵。 在一个实施例中，重采样器包括耦合到重采样器的输入的内插级，其接收表示沿位泵的接收路径传播的接收信号的至少一部分的一位输入信号，并产生多个 来自与一位输入信号相关联的至少两个输入采样的中间采样。 重采样器还包括耦合到内插级的选择级，其通过单个位的一个延迟线接收多个中间采样并选择一个，从而提供对应于振荡器的相位的输出采样。
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2.发明授权Oversampled A/D converter using filtered, cascaded noise shaping modulators 失效过采样A / D转换器使用滤波的级联噪声整形调制器
公开(公告)号：US4862169A
公开(公告)日：1989-08-29
申请号：US172823
申请日：1988-03-25
IPC分类号： H03M3/02
CPC分类号： H03M3/418
摘要： An oversampling A/D converter for high resolution data conversion is provided. An analog input signal is quantized into a digital equivalent value with a finite quantization error associated therewith in a first circuit portion. An analog low pass filter is inserted between the first circuit portion and a second circuit portion similar in function and circuitry to the first circuit portion. The second circuit portion functions to remove the error of the first circuit portion from an output signal by providing a signal component, which when added with the output of the first circuit portion cancels the error of the first circuit portion. The low pass filter provides attenuation of quantization error provided by the second circuit portion which results in an output signal with a significantly attenuated error.
摘要翻译： 提供了一种用于高分辨率数据转换的过采样A / D转换器。 在第一电路部分中，模拟输入信号被量化为与其相关联的有限量化误差的数字等效值。 在第一电路部分和第二电路部分之间插入模拟低通滤波器，其功能和电路类似于第一电路部分。 第二电路部分用于通过提供一个信号分量来消除第一电路部分的误差，当信号分量相加时，第一电路部分的输出消除第一电路部分的误差。 低通滤波器提供由第二电路部分提供的量化误差的衰减，这导致具有显着衰减误差的输出信号。
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公开(公告)号：US4843390A
公开(公告)日：1989-06-27
申请号：US159858
申请日：1988-02-24
IPC分类号： H03M3/02
摘要： An oversampled A/D converter which utilizes digital error correction is provided. In one form, the present invention is used with a sigma delta modulator having a plurality of rank ordered quantization loops, Each quantization loop contains an analog integrator circuit of predetermined gain which is subject to variation, thereby introducing errors. When the product of a reciprocal of the analog integrator gain and the gain of a digital gain stage of a subsequent quantization loop equals one, minimum noise exists in the data conversion. A digital gain control circuit is coupled to the digital gain stage for adjusting the gain of the digital gain stage during a calibration mode to provide minimum noise in the converter, thereby compensating for errors attributable to the analog integrator circuit.
摘要翻译： 提供了采用数字纠错的过采样A / D转换器。 在一种形式中，本发明与具有多个秩有序量化环路的Σ-Δ调制器一起使用。每个量化循环包含经受变化的预定增益的模拟积分电路，由此引入误差。 当模拟积分器的倒数乘积和后续量化环路的数字增益级的增益等于1时，数据转换中存在最小噪声。 数字增益控制电路耦合到数字增益级，用于在校准模式期间调整数字增益级的增益，以在转换器中提供最小的噪声，从而补偿归因于模拟积分器电路的误差。
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4.发明授权Digital tone detector using a ratio of two demodulators of differing frequency 失效数字音调检测器使用两个不同频率的解调器的比例
公开(公告)号：US4989169A
公开(公告)日：1991-01-29
申请号：US474607
申请日：1990-02-05
IPC分类号： H03D3/00
CPC分类号： H03D3/007 , H03D2200/0056
摘要： A digital tone detector receives a modulated input signal selectively containing at least one tone signal component. Two demodulator circuits each demodulate the input signal wherein one demodulator circuit operates at the predetermined frequency of the tone and the other demodulator circuit operates at the second harmonic. When the input tone has a low spectral harmonic power, a ratio of the demodulated outputs of the two demodulators reliably detects the presence of the tone in the input signal.
摘要翻译： 数字音调检测器接收选择性地包含至少一个音调信号分量的调制输入信号。 两个解调器电路各自解调输入信号，其中一个解调器电路以音调的预定频率工作，另一个解调器电路以二次谐波工作。 当输入音具有低频谱谐波功率时，两个解调器的解调输出的比率可靠地检测输入信号中的音调的存在。
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公开(公告)号：US06876699B1
公开(公告)日：2005-04-05
申请号：US09650851
申请日：2000-08-29
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： A filter circuit, method of configuring the filter circuit, and a bit pump and transceiver employing the circuit and method. In one embodiment, the filter circuit includes a noise prediction equalizer that generates a noise prediction equalizer coefficient during activation of the bit pump to reduce an intersymbol interference associated with a receive signal propagating along a receive path of the bit pump. The filter circuit also includes a decision feedback equalizer that generates a decision feedback equalizer coefficient during the activation of the bit pump to reduce the intersymbol interference associated with the receive signal. The noise prediction equalizer is concatenated with the decision feedback equalizer during showtime of the bit pump to form a precoder associated with a transmit path of the bit pump.
摘要翻译： 滤波电路，滤波器电路的配置方法以及采用该电路和方法的位泵和收发器。 在一个实施例中，滤波器电路包括噪声预测均衡器，其在位泵的激活期间产生噪声预测均衡器系数，以减少与沿着位泵的接收路径传播的接收信号相关联的符号间干扰。 滤波器电路还包括判决反馈均衡器，其在比特泵的激活期间产生判决反馈均衡器系数，以减少与接收信号相关联的符号间干扰。 在比特泵的显示时间期间，噪声预测均衡器与判决反馈均衡器连接以形成与比特泵的发送路径相关联的预编码器。
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公开(公告)号：US4999798A
公开(公告)日：1991-03-12
申请号：US486694
申请日：1990-03-01
CPC分类号： H03H17/0671
摘要： A transient-error free interpolating decimator utilizes only two comb filters. The decimator has an integrator circuit, which receives a digitized signal at a first clock rate, and a differentiator circuit. The differentiator includes first and second comb filters for down converting the digital signal at the first clock rate to a second clock rate, and for providing sample points at first and second outputs; the differentiator circuit and the integrator circuit comprise a decimation filter. A delay circuit provides coarse sampling phase adjustments by delaying the second clock rate by a predetermined number of first-clock cycles. A counter generates the second clock rate and provides coarse sampling phase adjustments by adding or deleting cycles of the first clock to or form the second clock. A multiplexer circuit swaps the two outputs when necessary to prevent transient errors generated in the differentiators from being observed. An interpolator circuit makes fine sampling phase adjustments by interpolation to provide an output that is transient-error free. The interpolator circuit includes a bypass circuit for bypassing the first output of the multiplexer circuit for preventing transient errors from being observed.
摘要翻译： 瞬态无错误内插抽取器仅使用两个梳状滤波器。 抽取器具有以第一时钟速率接收数字化信号的积分器电路和微分电路。 微分器包括第一和第二梳状滤波器，用于以第一时钟速率将数字信号下变频到第二时钟速率，并用于在第一和第二输出端提供采样点; 微分电路和积分器电路包括抽取滤波器。 延迟电路通过将第二时钟速率延迟预定数量的第一时钟周期来提供粗抽样相位调整。 计数器产生第二时钟速率，并且通过将第一时钟的周期添加或删除到第二时钟或者形成第二时钟来提供粗抽样相位调整。 必要时，多路复用器电路交换两个输出，以防止在微分器中产生的瞬态误差被观察到。 内插电路通过内插进行精细的采样相位调整，以提供无瞬态误差的输出。 内插器电路包括用于旁路多路复用器电路的第一输出的旁路电路，用于防止观察到瞬时错误。
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公开(公告)号：US4876543A
公开(公告)日：1989-10-24
申请号：US200475
申请日：1988-05-31
IPC分类号： H03M3/02
CPC分类号： H03M3/418
摘要： A noise shaping modulator for use in sigma delta modulation data conversion has two or more cascaded quantization loops. A first quantization loop is operated at a first sampling frequency and one or more higher order quantization loops are operated at a second sampling frequency. Due to speed limitations of analog circuitry in the first quantization loop, a significant improvement in signal to noise ratio may be achieved in a sigma delta modulation data converter by selecting the second sampling frequency higher than the first sampling frequency.
摘要翻译： 用于Σ-Δ调制数据转换的噪声整形调制器具有两个或多个级联量化环。 第一量化环路以第一采样频率工作，并且以第二采样频率操作一个或多个较高阶量化环路。 由于第一量化环路中的模拟电路的速度限制，可以通过选择高于第一采样频率的第二采样频率，在Σ-Δ调制数据转换器中实现信噪比的显着改善。
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8.发明授权Resampler for a bit pump and method of resampling a signal associated therewith 有权用于位泵的重采样器和与其相关联的信号重采样的方法公开(公告)号：US06973146B1
公开(公告)日：2005-12-06
申请号：US09652116
申请日：2000-08-29
CPC分类号： H04L7/0029 , H04B3/23 , H04L25/03057 , H04L25/03343 , H04L27/2626 , H04L27/2647 , H04L2025/03414
摘要： A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that selects one of the plurality of intermediate samples thereby providing an output sample that corresponds to a phase of an oscillator associated with the bit pump.
摘要翻译： 重采样器，对信号进行重采样的方法以及使用该信号的位泵。 在一个实施例中，重采样器包括耦合到重采样器的输入的内插级，其接收表示沿位泵的接收路径传播的接收信号的至少一部分的一位输入信号，并产生多个 来自与一位输入信号相关联的至少两个输入采样的中间采样。 重采样器还包括耦合到内插级的选择级，其选择多个中间样本之一，从而提供对应于与位泵相关联的振荡器的相位的输出样本。
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公开(公告)号：US5541864A
公开(公告)日：1996-07-30
申请号：US233814
申请日：1994-04-26
CPC分类号： H03H17/0614 , G06F17/17 , H03H17/0621
摘要： A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation is comprised of two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes a low precision set of filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients. A second, low pass filter section is provided for filtering the high frequency image energy at the output of the FIR filter to provide an overall filter response commensurate to that utilizing substantially higher precision FIR coefficients. The FIR filter coefficients utilized are restricted to the set of {-1, 0, +1} such that an arithmetic-free realization is provided wherein data is stored in a random access memory (68), with the non-zero coefficients for any interpolator output limited to a predetermined number. This predetermined number equals the maximum clock rate divided by the output sampling frequency. For each interpolator output, addresses of the associated data are stored in a ROM (72), which is operable to sequentially generate the addresses for accessing of data from a RAM (68). The sign is then changed, depending upon a sign change bit in the ROM (72), and then accumulated in an output accumulator (82). After all data is accessed from the RAM (68) for a given interpolator output, the accumulator (82) provides this output to the delta-sigma converter.
摘要翻译： 提供了一种低精度有限脉冲响应滤波器（FIR），用于在数字插值操作中进行滤波。 内插操作包括两个步骤：用于在输入序列中的样本之间散布零的采样率转换操作和滤除由该操作产生的图像的滤波步骤。 滤波操作利用FIR滤波器，其利用低精度滤波器系数集合来选择该滤波器系数来调谐频率响应，使得包括通带，过渡频带以及紧接在频带之后的阻带的部分的低端频率响应 过渡带提供与基本上更高精度的FIR滤波器系数相当的响应。 提供了第二低通滤波器部分，用于对在FIR滤波器的输出处的高频图像能量进行滤波，以提供与利用基本上更高精度的FIR系数相匹配的整体滤波器响应。 所使用的FIR滤波器系数被限制为{-1,0，+1}的集合，使得提供无算术实现，其中数据存储在随机存取存储器（68）中，其中非零系数用于任何 内插器输出限制为预定数量。 该预定数量等于最大时钟频率除以输出采样频率。 对于每个内插器输出，相关数据的地址被存储在ROM（72）中，ROM（72）可操作以顺序地生成用于从RAM（68）访问数据的地址。 然后根据ROM（72）中的符号改变位改变符号，然后累加在输出累加器（82）中。 在给定内插器输出之后，从RAM（68）访问所有数据之后，累加器（82）将该输出提供给Δ-Σ转换器。
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10.发明授权
公开(公告)号：US5257026A
公开(公告)日：1993-10-26
申请号：US870270
申请日：1992-04-17
摘要： A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta. coefficient is stored in a block (16) and is generated during a calibration cycle by a .delta. processor (39). The .delta. processor (39) receives the output of the compensation circuit (14) and the digital output from the summing junction (36) when the calibration multiplexer (10) sets the input to zero. A control circuit (40) controls the overall operation, with the calibration operation initiated in response to either an external signal on a line (30) or an internally generated signal. After calibration, the value of the .delta. coefficient is frozen and the calibration multiplexer (10) selects the analog input.
摘要翻译： 用于校准多电平Δ-Σ调制器（12）中的非线性的校准方法和装置包括在输入端上的校准多路复用器（10），用于在校准模式中选择用于输入到Δ-Σ调制器的零电压 （12）。 Δ-Σ调制器（12）具有三个电平，即+1,0，-1，向处理器（32）输入的+1电平，以及输入到处理器（34）的-1电平。 处理器（34）的输出被输入到补偿电路（14），该补偿电路将由-1处理器（34）产生的值偏移系数增量。 然后，补偿电路（14）的输出被输入到也接收处理器（32）的输出的求和结（36）的负输入，提供数字输出的求和结（36）的输出。 处理器（32）和（34）通过单独的累加器来实现，所述累加器在相关的滤波器系数和地之间切换存储在ROM（35）中的滤波器系数。 增量系数存储在块（16）中，并且在校准周期期间由增量处理器（39）产生。 当校准多路复用器（10）将输入设置为零时，Δ处理器（39）接收补偿电路（14）的输出和来自求和结（36）的数字输出。 控制电路（40）控制总体操作，其中响应于线路（30）上的外部信号或内部产生的信号启动校准操作。 校准后，delta系数的值被冻结，校准多路复用器（10）选择模拟输入。
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