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1.发明授权Resampler for a bit pump and method of resampling a signal associated therewith 有权用于位泵的重采样器和与其相关联的信号重采样的方法公开(公告)号：US07542536B2
公开(公告)日：2009-06-02
申请号：US11234361
申请日：2005-09-23
IPC分类号： H03K1/00
CPC分类号： H04L7/0029 , H04B3/23 , H04L25/03057 , H04L25/03343 , H04L27/2626 , H04L27/2647 , H04L2025/03414
摘要： A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that receives the plurality of intermediate samples via one delay line of single bits and select one thereof, thereby providing an output sample that corresponds to a phase of the oscillator.
摘要翻译： 重采样器，对信号进行重采样的方法以及使用该信号的位泵。 在一个实施例中，重采样器包括耦合到重采样器的输入的内插级，其接收表示沿位泵的接收路径传播的接收信号的至少一部分的一位输入信号，并产生多个 来自与一位输入信号相关联的至少两个输入采样的中间采样。 重采样器还包括耦合到内插级的选择级，其通过单个位的一个延迟线接收多个中间采样并选择一个，从而提供对应于振荡器的相位的输出采样。
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2.发明授权Resampler for a bit pump and method of resampling a signal associated therewith 有权用于位泵的重采样器和与其相关联的信号重采样的方法公开(公告)号：US06973146B1
公开(公告)日：2005-12-06
申请号：US09652116
申请日：2000-08-29
CPC分类号： H04L7/0029 , H04B3/23 , H04L25/03057 , H04L25/03343 , H04L27/2626 , H04L27/2647 , H04L2025/03414
摘要： A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that selects one of the plurality of intermediate samples thereby providing an output sample that corresponds to a phase of an oscillator associated with the bit pump.
摘要翻译： 重采样器，对信号进行重采样的方法以及使用该信号的位泵。 在一个实施例中，重采样器包括耦合到重采样器的输入的内插级，其接收表示沿位泵的接收路径传播的接收信号的至少一部分的一位输入信号，并产生多个 来自与一位输入信号相关联的至少两个输入采样的中间采样。 重采样器还包括耦合到内插级的选择级，其选择多个中间样本之一，从而提供对应于与位泵相关联的振荡器的相位的输出样本。
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公开(公告)号：US6055619A
公开(公告)日：2000-04-25
申请号：US797232
申请日：1997-02-07
申请人： Gregory Allen North , Douglas D. Gephardt , James D. Barnette , James D. Austin , Scott Thomas Haban , Thomas Saroshan David , Brian Christopher Kircher
发明人： Gregory Allen North , Douglas D. Gephardt , James D. Barnette , James D. Austin , Scott Thomas Haban , Thomas Saroshan David , Brian Christopher Kircher
CPC分类号： G10H7/002 , G06F3/162 , G10H2240/275
摘要： An audio information processing subsystem 200 is disclosed which includes a stream processor 100 for simultaneously processing multiple streams of audio data. Processing subsystem 200 also includes a program memory 202 coupled to stream processor 100 for storing instructions for controlling processing system 200 and a data memory 203/204 also coupled to stream processor 100. Additionally, a direct memory access circuitry 208 is provided for controlling direct memory accesses to a selected one of program memory 202 and data memory 203/204.
摘要翻译： 公开了一种音频信息处理子系统200，其包括用于同时处理多个音频数据流的流处理器100。 处理子系统200还包括耦合到流处理器100的程序存储器202，用于存储用于控制处理系统200的指令和还耦合到流处理器100的数据存储器203/204。另外，提供直接存储器访问电路208用于控制直接存储器 访问程序存储器202和数据存储器203/204中的所选择的一个。
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4.发明申请SYSTEM AND METHOD FOR SQUELCHING A RECOVERED CLOCK IN AN ETHERNET NETWORK 审中-公开用于在以太网网络中重建恢复时钟的系统和方法公开(公告)号：US20120224493A1
公开(公告)日：2012-09-06
申请号：US13471195
申请日：2012-05-14
申请人： Jason C. Rock , James D. Barnette
发明人： Jason C. Rock , James D. Barnette
CPC分类号： H04J3/0641
摘要： A system and method for squelching a recovered clock in an Ethernet network. In one embodiment the invention provides a method for squelching a recovered clock in an Ethernet network comprising a local node coupled to a remote node by a link, the method including receiving a descrambler status signal, receiving a remote receiver status signal, receiving a link status signal, and squelching the recovered clock signal based on the descrambler status signal, the remote receiver status signal, and the link status signal.
摘要翻译： 一种用于在以太网中抑制恢复时钟的系统和方法。 在一个实施例中，本发明提供了一种用于在包括通过链路耦合到远程节点的本地节点的以太网中抑制恢复的时钟的方法，所述方法包括：接收解扰器状态信号，接收远程接收器状态信号，接收链路状态 基于解扰器状态信号，远程接收器状态信号和链路状态信号来对恢复的时钟信号进行信号和静噪。
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5.发明授权公开(公告)号：US08179901B2
公开(公告)日：2012-05-15
申请号：US12029230
申请日：2008-02-11
申请人： Jason C. Rock , James D. Barnette
发明人： Jason C. Rock , James D. Barnette
IPC分类号： H04L12/28
CPC分类号： H04J3/0641
摘要： A system and method for squelching a recovered clock in an Ethernet network. In one embodiment the invention provides a method for squelching a recovered clock in an Ethernet network comprising a local node coupled to a remote node by a link, the method including receiving a descrambler status signal, receiving a remote receiver status signal, receiving a link status signal, and squelching the recovered clock signal based on the descrambler status signal, the remote receiver status signal, and the link status signal.
摘要翻译： 一种用于在以太网中抑制恢复时钟的系统和方法。 在一个实施例中，本发明提供了一种用于在包括通过链路耦合到远程节点的本地节点的以太网中抑制恢复的时钟的方法，所述方法包括：接收解扰器状态信号，接收远程接收器状态信号，接收链路状态 基于解扰器状态信号，远程接收器状态信号和链路状态信号来对恢复的时钟信号进行信号和静噪。
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6.发明申请METHOD FOR SWITCHING MASTER/SLAVE TIMING IN A 1000BASE-T LINK WITHOUT TRAFFIC DISRUPTION 有权在没有交通障碍的情况下在1000BASE-T链路中切换主/从时序的方法公开(公告)号：US20110170645A1
公开(公告)日：2011-07-14
申请号：US13005515
申请日：2011-01-12
CPC分类号： H04J3/0641 , H04L7/0337 , H04L12/42 , H04L12/437
摘要： A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins receive timing recovery. The slave freezes its receive timing recovery and locks its transmit clock. The master device transitions its transmit timing to use the recovered receive clock. The slave gradually switches to transmitting using its local clock signal. The method may be used in synchronous Ethernet networks.
摘要翻译： 一种方法在通信网络中切换主/从定时，而不会流量中断。 该方法包括通知从站的定时丢失的主设备。 主设备另外开始从本地参考时钟定时发送，并开始接收定时恢复。 从机冻结其接收定时恢复并锁定其传输时钟。 主设备转换其发送定时以使用恢复的接收时钟。 从机逐渐切换到使用其本地时钟信号发送。 该方法可用于同步以太网。
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7.发明申请公开(公告)号：US20090201924A1
公开(公告)日：2009-08-13
申请号：US12029230
申请日：2008-02-11
申请人： Jason C. Rock , James D. Barnette
发明人： Jason C. Rock , James D. Barnette
CPC分类号： H04J3/0641
摘要： A system and method for squelching a recovered clock in an Ethernet network. In one embodiment the invention provides a method for squelching a recovered clock in an Ethernet network comprising a local node coupled to a remote node by a link, the method including receiving a descrambler status signal, receiving a remote receiver status signal, receiving a link status signal, and squelching the recovered clock signal based on the descrambler status signal, the remote receiver status signal, and the link status signal.
摘要翻译： 一种用于在以太网中抑制恢复时钟的系统和方法。 在一个实施例中，本发明提供了一种用于在包括通过链路耦合到远程节点的本地节点的以太网中抑制恢复的时钟的方法，所述方法包括：接收解扰器状态信号，接收远程接收器状态信号，接收链路状态 基于解扰器状态信号，远程接收器状态信号和链路状态信号来对恢复的时钟信号进行信号和静噪。
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8.发明申请SYSTEM AND METHOD FOR DETECTING EARLY LINK FAILURE IN AN ETHERNET NETWORK 审中-公开用于检测以太网中早期链路故障的系统和方法公开(公告)号：US20090201821A1
公开(公告)日：2009-08-13
申请号：US12029195
申请日：2008-02-11
IPC分类号： H04L12/26
CPC分类号： H04L12/66 , H04L41/0677 , H04L43/0817
摘要： A system and method for providing an early indication of link failure in an Ethernet network. In some embodiments an Ethernet PHY determines a link failure if the PHY loses descrambler synchronization, if remote receiver status is determined to indicate a remote receiver failure, or if link status indicates a link failure.
摘要翻译： 一种在以太网网络中提供链路故障早期指示的系统和方法。 在一些实施例中，如果远程接收机状态被确定为指示远程接收机故障，或者如果链路状态指示链路故障，则以太网PHY确定如果PHY失去解扰器同步的链路故障。
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9.发明授权Interpolator, a resampler employing the interpolator and method of interpolating a signal associated therewith 有权Interpolator，采用内插器的重采样器和内插与之相关联的信号的方法公开(公告)号：US06970511B1
公开(公告)日：2005-11-29
申请号：US09650850
申请日：2000-08-29
申请人： James D. Barnette
发明人： James D. Barnette
CPC分类号： H03H17/0621 , H03H2218/06
摘要： An interpolator, method of interpolating a one-bit signal and resampler employing the interpolator and method. The interpolator employs a cascaded architecture to interpolate a one-bit input signal received at an input thereof. In one embodiment, the interpolator includes a multiple order interpolation filter that generates a sample range from at least three input samples associated with the one-bit input signal. The interpolator further includes a linear interpolation filter, associated with the multiple order interpolation filter, that develops a plurality of samples within the sample range.
摘要翻译： 内插器，内插一位信号的方法和采用内插器和方法的重采样器。 内插器采用级联架构来内插在其输入处接收的一位输入信号。 在一个实施例中，内插器包括多级内插滤波器，其从与一比特输入信号相关联的至少三个输入样本产生采样范围。 内插器还包括与多阶内插滤波器相关联的线性内插滤波器，其在采样范围内产生多个采样。
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10.发明授权Method for switching master/slave timing in a 1000BASE-T link without traffic disruption 有权用于在没有流量中断的情况下在1000BASE-T链路中切换主/从定时的方法公开(公告)号：US08923341B2
公开(公告)日：2014-12-30
申请号：US13005515
申请日：2011-01-12
IPC分类号： H04L7/00 , H04J3/06 , H04L12/42 , H04L12/437
CPC分类号： H04J3/0641 , H04L7/0337 , H04L12/42 , H04L12/437
摘要： A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins receive timing recovery. The slave freezes its receive timing recovery and locks its transmit clock. The master device transitions its transmit timing to use the recovered receive clock. The slave gradually switches to transmitting using its local clock signal. The method may be used in synchronous Ethernet networks.
摘要翻译： 一种方法在通信网络中切换主/从定时，而不会流量中断。 该方法包括通知从站的定时丢失的主设备。 主设备另外开始从本地参考时钟定时发送，并开始接收定时恢复。 从机冻结其接收定时恢复并锁定其传输时钟。 主设备转换其发送定时以使用恢复的接收时钟。 从机逐渐切换到使用其本地时钟信号发送。 该方法可用于同步以太网。
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