公开(公告)号：US4034340A

公开(公告)日：1977-07-05

申请号：US693869

申请日：1976-06-08

申请人： Marcello Sant'Agostino

发明人： Marcello Sant'Agostino

IPC分类号： H04L1/02 ,  H04L1/24 ,  H04L25/04 ,  H04L25/06 ,  H03K13/32

CPC分类号： H04L25/065 ,  H04L1/02 ,  H04L1/241 ,  H04L25/063

摘要： At a receiver for binary or other digital message signals, the incoming signals are fed in parallel to a first decision network with a relatively low threshold and a second decision network with a relatively high threshold, the latter being adjustable. The output of the first decision network is delivered to a utilization circuit and in parallel therewith, together with the output of the second decision network, to a comparator emitting a pseudo-error pulse in response to any divergence in the two outputs. A counter stepped by the pseudo-error pulses, upon reaching a predetermined count, triggers a pulse generator producing a binary voltage v.sub.i whose mean value v.sub.u, obtained by integration, is a measure of signal degradation. Under the control of this mean value v.sub.u the threshold of the second decision network is automatically varied in the opposite sense to maintain a substantially constant pseudo-error rate. Another comparator, on detecting a lowering of this threshold beyond a permissible minimum, triggers an alarm circuit to bring about a manual or automatic switchover to another transmission channel. The voltage v.sub.u or its reciprocal, the variable threshold, may be continuously monitored by visual inspection and/or automatic recording.

摘要翻译： 在用于二进制或其他数字消息信号的接收机处，输入信号被并行地馈送到具有相对较低阈值的第一决策网络和具有相对较高阈值的第二决策网络，后者可调整。 第一决策网络的输出与第二决策网络的输出一起被传送到利用电路并且与第二决策网络的输出相对应于两个输出中的任何发散而发出伪错误脉冲的比较器。 通过伪误差脉冲步进的计数器在达到预定计数时触发产生二进制电压vi的脉冲发生器，其中通过积分获得的平均值vu是信号劣化的量度。 在该平均值vu的控制下，第二判定网络的阈值在相反的意义上自动变化，以维持基本上恒定的伪错误率。 另一个比较器在检测到该阈值的下降超过允许的最小值时触发报警电路，以便手动或自动切换到另一个传输通道。 可以通过目视检查和/或自动记录来连续监测电压vu或其倒数，可变阈值。

公开(公告)号：US3509279A

公开(公告)日：1970-04-28

申请号：US3509279D

申请日：1967-05-22

申请人： COLLINS RADIO CO

发明人： MARTIN DONALD L ,  OLSON OSCAR P ,  HUTCHINSON WILLIAM M

IPC分类号： H03K5/24 ,  H04L25/06 ,  H04L13/18 ,  H04L15/26

CPC分类号： H04L25/065 ,  H03K5/24 ,  H04L25/061

公开(公告)号：US09712351B2

公开(公告)日：2017-07-18

申请号：US14011470

申请日：2013-08-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Chang Soon Park ,  Young Jun Hong ,  Joon Seong Kang ,  Jong Han Kim

IPC分类号： H04L27/06 ,  H04L25/06

CPC分类号： H04L25/065 ,  H04L25/063 ,  H04L25/067 ,  H04L27/06

摘要： An apparatus and method are provided to adaptively set a threshold to detect a transmission symbol. The apparatus and method calculate detection parameters to determine the threshold to detect the transmission symbol based on probability distribution parameters, which determine a statistical probability distribution of an input signal. The apparatus and method adaptively detect a present transmission symbol using a previously detected transmission symbol and the detection parameters.

公开(公告)号：US20150219697A1

公开(公告)日：2015-08-06

申请号：US14173241

申请日：2014-02-05

申请人： Nvidia Corporation

发明人： Victor Chen ,  Jesse Max Guss ,  Craig Ross ,  Kevin Wong ,  Jason Kwok-san Lee

IPC分类号： G01R19/165 ,  G06T1/20

CPC分类号： G01R19/165 ,  H03K19/00 ,  H03K19/0002 ,  H04L25/00 ,  H04L25/065

摘要： An integrated circuit (IC) based detection circuit for determining a strap value and a method of detecting a digital strap value. In one embodiment, the detection circuit includes: (1) a first receiver including transistors having first electrical characteristics that define a first threshold for the first receiver, the first receiver operable to generate a first binary digit based on an input signal and the first threshold and (2) a second receiver including transistors having second electrical characteristics that differ from the first electrical characteristics and define a second threshold for the second receiver that is lower than the first threshold, the second receiver operable to generate a second binary digit based on the input signal and the second threshold, the first and second binary digits indicating whether the strap value lies above the first threshold, between the first and second thresholds or below the second threshold.

摘要翻译： 一种用于确定条带值的基于集成电路（IC）的检测电路和一种检测数字带值的方法。 在一个实施例中，检测电路包括：（1）第一接收器，包括具有第一电特性的晶体管，第一电特性限定第一接收器的第一阈值，第一接收器可操作以基于输入信号和第一阈值产生第一二进制数字 和（2）第二接收器，包括具有不同于第一电特性的第二电特性的晶体管，并且限定低于第一阈值的第二接收器的第二阈值，第二接收器可操作以基于 输入信号和第二阈值，第一和第二二进制数字指示带值是否高于第一阈值，在第一和第二阈值之间或低于第二阈值。

公开(公告)号：US08644434B2

公开(公告)日：2014-02-04

申请号：US13240895

申请日：2011-09-22

申请人： Sanjib Paul

发明人： Sanjib Paul

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H04L25/065

摘要： An apparatus for performing sequence detection on a stream of incoming bits comprises a memory and circuitry coupled to the memory. The circuitry is operative, for each bit of the stream of incoming bits, to overwrite a first binary number presently stored in the memory with a second binary number, and to provide an output indicative of when the second binary number is equal to a predetermined value. The output indicative of when the second binary number is equal to the predetermined value is, in turn, indicative of when a binary number constructed by the stream of incoming bits is divisible by a prescribed integer.

摘要翻译： 用于对输入比特流执行序列检测的装置包括耦合到存储器的存储器和电路。 对于输入比特流的每个比特来说，该电路可以用当前存储在存储器中的第二个二进制数字来重写当前存储的第二个二进制数，并且提供一个指示第二个二进制数何时等于预定值的输出 。 指示第二二进制数何时等于预定值的输出又指示何时由输入比特流构成的二进制数可被规定的整数整除。

公开(公告)号：US07443927B2

公开(公告)日：2008-10-28

申请号：US11761439

申请日：2007-06-12

申请人： Yi-Yang Chang

发明人： Yi-Yang Chang

IPC分类号： H04L27/00 ,  H04L27/06 ,  H04L23/00

CPC分类号： H04L25/0272 ,  H04L25/065

摘要： A signal detector comprises a signal translator, a data signal detector, a clock signal detector and an inputting control circuit for detecting abnormal clock and data signals. The signal translator respectively converts differential data signals and differential clock signal into a single data signal and a single clock signal. The data signal detector outputs a data detecting signal according to the single data signal. The clock signal detector outputs a clock detecting signal according to the single clock signal. The interrupting control circuit receives the data detecting signal and outputs a shutdown signal when the single data signal is at high voltage level over a predefined ratio. The interrupting control circuit also receives the clock detecting signal and outputs the shutdown signal when the single clock signal abnormally disappears.

摘要翻译： 信号检测器包括信号转换器，数据信号检测器，时钟信号检测器和用于检测异常时钟和数据信号的输入控制电路。 信号转换器分别将差分数据信号和差分时钟信号转换为单个数据信号和单个时钟信号。 数据信号检测器根据单个数据信号输出数据检测信号。 时钟信号检测器根据单个时钟信号输出时钟检测信号。 中断控制电路接收数据检测信号，并且当单个数据信号以预定比例处于高电压电平时，输出关闭信号。 当单个时钟信号异常消失时，中断控制电路还接收时钟检测信号并输出​​关断信号。

公开(公告)号：US06735260B1

公开(公告)日：2004-05-11

申请号：US09550569

申请日：2000-04-17

申请人： Oren Eliezer ,  Yaron Kaufmann ,  Yasuhiro Satoh

发明人： Oren Eliezer ,  Yaron Kaufmann ,  Yasuhiro Satoh

IPC分类号： H04L2722

CPC分类号： H04L25/065 ,  H04L25/062

摘要： An adaptive data slicer which functions to adapt to changes in the properties of a signal input thereto by producing a near optimal slicing threshold in accordance with the input signal for use in a decision circuit. The slicing level is considered optimal when its use in the decision circuit minimizes the bit error probability. The data slicer utilizes two peak detectors, a maximum peak detector for detecting the highest levels of the input signal and a minimum peak detector for detecting the lowest levels of the input signal.

摘要翻译： 一种自适应数据限幅器，其通过根据用于判决电路的输入信号产生接近最佳限幅阈值来适应输入信号的属性变化。 当其在判决电路中的使用将误码概率最小化时，切片电平被认为是最佳的。 数据限幅器使用两个峰值检测器，一个用于检测输入信号的最高电平的最大峰值检测器和用于检测输入信号的最低电平的最小峰值检测器。

公开(公告)号：US5410569A

公开(公告)日：1995-04-25

申请号：US931176

申请日：1992-08-19

申请人： Scott F. Halozan

发明人： Scott F. Halozan

IPC分类号： H04L25/06 ,  H04L25/49

CPC分类号： H04L25/065 ,  H04L25/062 ,  H04L25/066 ,  H04L25/4917

摘要： A receiver for receiving transmitted digital signals including either two level or four level symbols that are interleaved in a predetermined pattern in a frame format consisting of a plurality of successive data segments. The symbols are converted into ten bit numbers that are soft sliced to generate four bit numbers representing ranges of values within which each ten bit number may fall. The data represented by the four bit numbers is deinterleaved, a birate flag is generated that identifies the nature of each four bit number, i.e. whether it represents a two level symbol or a four level symbol, and a hard slicer operates, in response to the birate flag, for converting each of the four bit numbers to corresponding two bit binary outputs.

摘要翻译： 一种用于接收发送的数字信号的接收机，包括以由多个连续数据段组成的帧格式以预定模式进行交织的两个电平或四个电平符号。 符号被转换成十位数，它们是软分片，以产生表示每十位数可能落在其中的值的范围的四位数。 由四位数字表示的数据被解交织，生成标识每个四位数的性质的双向标志，即它是否表示二级符号或四级符号，并且硬切片器响应于 双向标志，用于将四个位数中的每一个转换为相应的二位二进制输出。

公开(公告)号：US5247211A

公开(公告)日：1993-09-21

申请号：US835928

申请日：1992-03-02

申请人： Shigeyuki Sakura

发明人： Shigeyuki Sakura

IPC分类号： H03K5/08 ,  H03F1/02 ,  H03F3/08 ,  H04B10/07 ,  H04B10/2507 ,  H04B10/293 ,  H04B10/564 ,  H04B10/572 ,  H04L25/02 ,  H04L25/03 ,  H04L25/06

CPC分类号： H03F1/0222 ,  H03F3/087 ,  H04B10/695 ,  H04L25/062 ,  H04L25/065

摘要： A light-receiving circuit according to the present invention incorporates an amplifier 12 having differential output terminals, and it is intended that normal-phase and inverted-phase outputs (Vp, -Vp) of the amplifier 12 be supplied to a comparator 34 at an appropriate threshold level at all times. To achieve this intention, a peak-value voltage (Vi) of the normal-phase and inverted-phase outputs of the amplifier 12 is detected by a peak value detector 26, and is converted into a current by means of a voltage-current converter 28 having a mutual conductance of gm. The voltage-current converter 28 has differential output terminals, from which a normal-phase output (I.sub.+ =gm.Vi) and an inverted-phase output (I.sub.- =gm.Vi) are produced, respectively. The currents (I.sub.+, I.sub.-) are converted into voltages by means of resistors R10 and R12. The resultant currents are subtracted from the normal-phase and inverted-phase outputs (Vp, -Vp) of the amplifier 12, respectively, so that the normal-phase and inverted-phase outputs (Vp, -Vp) are shifted in level to the degree corresponding to the same voltage. The signals, thus shifted in level, are supplied to the normal-phase and inverted-phase input terminals of the comparator 34.

摘要翻译： PCT No.PCT / JP91 / 00883 Sec。 371日期：1992年3月2日 102（e）1992年3月2日PCT PCT 1991年7月1日PCT公布。 出版物WO92 / 01348 根据本发明的光接收电路包括具有差分输出端的放大器12，并且意图是放大器12的正相和反相输出（Vp，-Vp）为 始终以适当的阈值提供给比较器34。 为了实现该目的，通过峰值检测器26检测放大器12的正相和反相输出的峰值电压（Vi），并通过电压 - 电流转换器 28具有gm的相互电导。 电压 - 电流转换器28具有分别产生正相输出（I + = gm.Vi）和反相输出（I- = gm.Vi）的差分输出端子。 电流（I +，I-）通过电阻R10和R12转换成电压。 分别从放大器12的正相和反相输出（Vp，-Vp）中减去所得到的电流，使得正相和反相输出（Vp，-Vp）的电平被移位到 相当于相同电压的程度。 因此，电平移位的信号被提供给比较器34的正相和反相输入端。

公开(公告)号：US5142554A

公开(公告)日：1992-08-25

申请号：US607989

申请日：1990-10-31

申请人： Bradley C. Stribling ,  Roger J. O. Eline

发明人： Bradley C. Stribling ,  Roger J. O. Eline

IPC分类号： H03K5/08 ,  H04L25/06

CPC分类号： H04L25/065 ,  H03K5/082 ,  H04L25/062

摘要： A comparator-based digital data separator is modified to operate in noisy signal environments, with signals characterized by extreme duty cycle. A demodulated binary signal is passed through a pair of diodes which produce a slack voltage. The signal is then passed through an RC low-pass filter, and is finally connected to an input of the comparator as the reference voltage. The low-pass filter, which provides the D.C. averaged voltage to the threshold comparator, receives current into its own input only when the demodulated signal excursions exceed the existing threshold voltage by more than the slack voltage. Consequently, assuming there exists a sufficiently large recovered signal, the voltage being used as the decision threshold will remain separated from the recovered signal excursion peaks by at least the amount of slack voltage. In so doing, the binary data separation is given improved noise immunity and reduced sensitivity to duty cycle variations.

摘要翻译： 基于比较器的数字数据分离器被修改为在噪声信号环境中工作，信号的特征在于极端的占空比。 解调的二进制信号通过产生松弛电压的一对二极管。 然后，该信号通过RC低通滤波器，最后连接到比较器的输入作为参考电压。 只有当解调信号偏移超过现有阈值电压超过松弛电压时，低通滤波器才能向阈值比较器提供直流电平均电压，从而将电流接收到自己的输入端。 因此，假设存在足够大的恢复信号，则用作判定阈值的电压将与恢复的信号偏移峰值保持至少一定的松弛电压。 在这样做时，二进制数据分离被赋予改进的抗噪声性能并降低对占空比变化的灵敏度。