公开(公告)号：US08612840B2

公开(公告)日：2013-12-17

申请号：US13068786

申请日：2011-05-19

申请人： Natalja Kehl

发明人： Natalja Kehl

IPC分类号： G06F11/00 ,  H03M1/00

CPC分类号： H03M1/0687 ,  H03M1/365

摘要： For detecting an error of an A/D converter, which is designed to generate at least one digital output signal, which includes a quantity of output data bits, based on at least one analog input signal, and during a conversion, to generate a thermometer code which includes a quantity T of output data values, the detection method includes: ascertaining a first parity directly for the output data bits of the output signal; making a prediction for the output data bits on the basis of the T output data values of the thermometer code; ascertaining a second parity, which is a reverse of the first parity, for the predicted output data bits; and detecting an error for the A/D converter when both the first and second parities are identical.

摘要翻译： 为了检测A / D转换器的误差，其被设计为基于至少一个模拟输入信号，并且在转换期间产生包括一定数量的输出数据位的至少一个数字输出信号，以产生温度计 代码，其包括输出数据量的数量T，所述检测方法包括：确定所述输出信号的输出数据位的第一奇偶校验; 基于温度计代码的T个输出数据值对输出数据位进行预测; 确定预测输出数据位的与第一奇偶校验相反的第二奇偶校验; 以及当所述第一和第二奇偶校验都相同时，检测所述A / D转换器的误差。

公开(公告)号：US20090006923A1

公开(公告)日：2009-01-01

申请号：US11768527

申请日：2007-06-26

申请人： Alan G. Gara ,  Dong Chen ,  Philip Heidelberger ,  Martin Ohmacht

发明人： Alan G. Gara ,  Dong Chen ,  Philip Heidelberger ,  Martin Ohmacht

IPC分类号： H03M13/00

CPC分类号： G06F11/1076 ,  G06F11/1064 ,  G06F2212/403 ,  H03M1/0687 ,  H03M13/13 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/29 ,  H03M13/616

摘要： A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

摘要翻译： 公开了用于为给定的n位组提供组合的错误代码保护和子组奇偶校验保护的方法和系统。 该方法包括以下步骤：识别用于所述错误保护的冗余位的数量m; 并且构造矩阵P，其中将所述给定的n个比特组与P相乘产生m个冗余纠错码（ECC）保护比特，并且两列P为所述给定组n比特的子组提供奇偶校验保护。 在本发明的优选实施例中，矩阵P是通过产生具有三个或更多个奇数个元素的m位宽向量的排列而构成的，其中值为1的元素和其他元素的值为零; 并将所述向量分配给矩阵P的行。

公开(公告)号：US06965332B2

公开(公告)日：2005-11-15

申请号：US10376467

申请日：2003-02-28

申请人： Katsufumi Nakamura ,  Steven Decker

发明人： Katsufumi Nakamura ,  Steven Decker

IPC分类号： H03M1/06 ,  H03M1/16 ,  H03M1/10

CPC分类号： H03M1/0687 ,  H03M1/0607 ,  H03M1/167

摘要： One embodiment of the invention is directed to a method comprising an act of performing digital correction of an offset in a system comprising an analog-to-digital converter (ADC) having a usable input range that is greater than a nominal input range, wherein the offset exists at an input of the ADC. Another embodiment of the invention is directed to a system comprising an ADC having a usable input range that is greater than a nominal input range, wherein an offset exists at an input of the ADC and the offset is corrected using digital correction.

摘要翻译： 本发明的一个实施例涉及一种方法，其包括在包括具有大于标称输入范围的可用输入范围的模拟 - 数字转换器（ADC）的系统中执行偏移的数字校正的动作，其中， 偏移存在于ADC的输入端。 本发明的另一个实施例涉及一种包括具有大于标称输入范围的可用输入范围的ADC的系统，其中在ADC的输入处存在偏移，并且使用数字校正来校正偏移。

公开(公告)号：US06703951B2

公开(公告)日：2004-03-09

申请号：US09906797

申请日：2001-07-18

申请人： Sanroku Tsukamoto

发明人： Sanroku Tsukamoto

IPC分类号： H03M716

CPC分类号： H03M1/0687 ,  H03M1/0809 ,  H03M1/1095 ,  H03M1/365 ,  H03M13/47

摘要： A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

摘要翻译： 高速A / D转换器包括用于将温度计代码转换为灰度代码的一系列编码器部分和用于检测灰度代码中的错误信号的误差信号产生部分，并产生指示这种混淆误差的误差信号。 误差校正部分根据误差信号校正灰度代码中的错误。 然后将经校正的灰度码转换为具有灰度码的二进制码到二进制码转换器。 当将高速A / D转换器并入半导体器件中时，可以使用具有相对于输入模拟信号连续变化的相位的采样时钟来测试A / D转换器，以对模拟信号进行采样，然后评估 相应产生的数字信号。

公开(公告)号：US20030179119A1

公开(公告)日：2003-09-25

申请号：US10376467

申请日：2003-02-28

申请人： Analog Devices, Inc.

发明人： Katsufumi Nakamura ,  Steven Decker

IPC分类号： H03M001/06

CPC分类号： H03M1/0687 ,  H03M1/0607 ,  H03M1/167

摘要： One embodiment of the invention is directed to a method comprising an act of performing digital correction of an offset in a system comprising an analog-to-digital converter (ADC) having a usable input range that is greater than a nominal input range, wherein the offset exists at an input of the ADC. Another embodiment of the invention is directed to a system comprising an ADC having a usable input range that is greater than a nominal input range, wherein an offset exists at an input of the ADC and the offset is corrected using digital correction.

摘要翻译： 本发明的一个实施例涉及一种方法，其包括在包括具有大于标称输入范围的可用输入范围的模拟 - 数字转换器（ADC）的系统中执行偏移的数字校正的动作，其中， 偏移存在于ADC的输入端。 本发明的另一个实施例涉及一种包括具有大于标称输入范围的可用输入范围的ADC的系统，其中在ADC的输入处存在偏移，并且使用数字校正来校正偏移。

公开(公告)号：US5995035A

公开(公告)日：1999-11-30

申请号：US990335

申请日：1997-12-15

申请人： Svante Signell ,  Bengt Erik Jonsson ,  Helge Stenstrom ,  Nianxiong Tan

发明人： Svante Signell ,  Bengt Erik Jonsson ,  Helge Stenstrom ,  Nianxiong Tan

IPC分类号： H03M1/06 ,  H03M1/40 ,  H03M1/66 ,  H03M1/72 ,  H03M1/34

CPC分类号： H03M1/0687 ,  H03M1/0682 ,  H03M1/403 ,  H03M1/667

摘要： Cyclic A/D-conversion of an analog input signal is performed according to a new and inventive recursive algorithm which generates a Gray coded digital output signal. In cyclic A/D-conversion, the output bits are generated cyclically, one by one. According to the inventive Gray coding algorithm, the analog input signal is cyclically subjected to a sample and hold operation, selectively, depending on the previously generated output bit, to a signal inversion, to an amplification by two, and to an addition of a predetermined reference signal. In a cyclic A/D-converter architecture based on the recursive Gray coding algorithm according to the invention, the accumulation of offset errors will generally be very low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations which further improve the performance of the cyclic A/D-converter according to the invention.

摘要翻译： 根据产生灰度编码数字输出信号的新的和本发明的递归算法来执行模拟输入信号的循环A / D转换。 在循环A / D转换中，输出位逐个生成。 根据本发明的格雷编码算法，模拟输入信号根据先前产生的输出位选择性地进行采样和保持操作，信号反相，放大倍数，以及预定的 参考信号。 在基于根据本发明的递归灰度编码算法的循环A / D转换器架构中，偏移误差的积累通常将非常低。 此外，信号反转被数字控制的事实使得能够实现根据本发明的循环A / D转换器的性能的高精度实现。

公开(公告)号：US3487401A

公开(公告)日：1969-12-30

申请号：US3487401D

申请日：1966-07-18

申请人： MOORE REED IND LTD

发明人： EVANS DAVID SILVESTER

IPC分类号： H03M1/00 ,  H03M1/06 ,  H03M1/26 ,  H04L3/00 ,  H03K13/00

CPC分类号： H03M1/0687 ,  H03M1/26

摘要： 1,157,641. Selective signalling. MOORE REED (INDUSTRIAL) Ltd. 15 July, 1966 [28 July, 1965], No. 32250/65. Heading G4H. A shaft 64, Fig. 6, position digitizer includes a 10 -3 stage 61 in which brushes 0/9, 1/8, 2/7, 3/6, 4/5 and A, B, C, C o , C e and COM, Fig. 5, are moved over stationary conductive segments 53, 54, 55, and 10 -2 and 10-1 stages 62, 63 in which coded scales (e.g. as in Fig. 7, not shown, or as in Specification 1,135,204, which is referred to) are moved past stationary brushes, the arrangement being such that each stage produces a " choosing signal " which selects which brushes in the next higher stage are to be operative. The lowest denominational stage 61, Fig. 6, includes two brushes A, B, Fig. 5, whose outputs when suitably combined (Fig. 2, not shown) produce inverse signals a, b, Fig. 3a, which are used to energize the C e and C 0 brushes respectively, Fig. 5, so that each numbered brush (e.g. 0/9) produces a signal when in a position corresponding to either of its numbers, the ambiguity being resolved by reference to brush C.

公开(公告)号：US12119836B2

公开(公告)日：2024-10-15

申请号：US18186657

申请日：2023-03-20

申请人： NetApp Inc.

发明人： Ram Kesavan ,  Matthew Fontaine Curtis-Maury ,  Abdul Basit ,  Vinay Devadas ,  Ananthan Subramanian ,  Mark Smith

IPC分类号： H03M1/12 ,  G06F3/06 ,  G06F16/901 ,  H03M1/06

CPC分类号： H03M1/0687 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0685 ,  G06F16/9027 ,  H03M1/0695

摘要： Techniques are provided for compacting indirect blocks. For example, an object is represented as a structure including data blocks within which data of the object is stored and indirect blocks including block numbers of where the data blocks are located in storage. Block numbers within a set of indirect blocks are compacted into a compacted indirect block including a base block number, a count of additional block numbers after the base block number in the compacted indirect block, and a pattern of the block numbers in the compacted indirect block. The compacted indirect block is stored into memory for processing access operations to the object. Storing compacted indirect blocks into memory allows for more block numbers to be stored within memory.

公开(公告)号：US20240039542A1

公开(公告)日：2024-02-01

申请号：US18482925

申请日：2023-10-09

申请人： Texas Instruments Incorporated

发明人： Michael Henderson Perrott ,  Robert Karl Butler

IPC分类号： H03L7/08 ,  H03L7/107 ,  H03L7/081 ,  H03L7/187 ,  H03L7/04 ,  G11C11/4093 ,  G11C11/4099 ,  H03M1/06 ,  H03M1/08 ,  H03M1/18

CPC分类号： H03L7/0807 ,  H03L7/1072 ,  H03L7/0816 ,  H03L7/187 ,  H03L7/04 ,  G11C11/4093 ,  G11C11/4099 ,  H03M1/0626 ,  H03M1/0687 ,  H03M1/0836 ,  H03M1/182

摘要： In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.

公开(公告)号：US11791831B1

公开(公告)日：2023-10-17

申请号：US18320644

申请日：2023-05-19

申请人： Apogee Semiconductor, Inc.

发明人： David A. Grant ,  Mark Hamlyn

IPC分类号： H03M7/00 ,  H03M7/34 ,  H03M1/12 ,  H03M1/06 ,  H03K19/08 ,  H03K19/23

CPC分类号： H03M1/0687 ,  H03K19/0813 ,  H03K19/23

摘要： Systems and methods for fault-tolerant threshold circuits used in converting an analog input to a single-bit digital output employ N-modular redundancy of either inverting or non-inverting threshold circuits whose inputs are connected to a single input, and apply majority voting of their outputs to provide correction of transient or permanent faults in up to floor[(N−1)/2] of the individual threshold circuits. Using summation to perform analog majority voting averages the N threshold circuit outputs and provides resilience to single-event transients, but may exhibit an output characteristic having intermediate voltage levels. A digital majority voter having N inputs connected to the outputs of N threshold circuits restores well-defined logic levels and clean hysteresis for Schmitt trigger threshold circuits. A single point of failure at the digital majority voter may be eliminated using an analog majority voter to sum the outputs of three or more redundant digital majority voters.