公开(公告)号：US08570093B2

公开(公告)日：2013-10-29

申请号：US13711447

申请日：2012-12-11

申请人： Silergy Semiconductor Technology (Hangzhou) Ltd

发明人： Michael Grimm ,  Jun Chen

IPC分类号： H03K17/687

CPC分类号： H03K17/102 ,  G05F3/02 ,  H02M3/33507 ,  H03K5/084

摘要： The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors.

摘要翻译： 本发明涉及使用MOS晶体管的共源共栅电路。 在一个实施例中，自适应级联电路可以包括：（i）主MOS晶体管; （ii）与主MOS晶体管的漏极串联耦合的n个自适应MOS晶体管，其中n可以是大于1的整数; （iii）连接到n个自适应MOS晶体管的栅极的关断钳位电路，其中关断钳位电路可以具有不大于主MOS晶体管和n个自适应MOS的额定栅极 - 漏极电压的（n + 1）关断钳位电压 晶体管 以及（iv）n个导通钳位电路，其对应于自适应MOS晶体管的栅极耦合，其中n个导通钳位电路可以具有不大于自适应MOS晶体管的导通阈值电压的n导通钳位电压。

公开(公告)号：US07859354B1

公开(公告)日：2010-12-28

申请号：US11960343

申请日：2007-12-19

申请人： Shuxian Chen ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： H03B27/00 ,  H03B5/24

CPC分类号： H03K3/0315 ,  G06F1/08 ,  H03K5/084 ,  H03K5/1252

摘要： Ring oscillator circuitry is provided. The ring oscillator circuitry may include a loop of inverters. A control gate may be interposed in the loop to control operation of the loop. The control gate may be activated using a ring oscillator trigger signal. During application of the trigger signal, the trigger signal may become degraded due to circuit parasitics. Trigger signal conditioning circuitry may be used to remove noise from the degraded trigger signal. A version of the trigger signal that has been conditioned by the trigger signal conditioning circuitry may be applied to a control input of the control gate. The trigger signal conditioning circuitry may include a low pass filter, a hysteresis circuit, and a two-stage buffer. The two-stage buffer may be formed from transistors with the same characteristics as the transistors in the inverters of the ring oscillator loop.

摘要翻译： 提供环形振荡器电路。 环形振荡器电路可以包括一个反相器回路。 控制栅极可以插入到环路中以控制环路的操作。 可以使用环形振荡器触发信号来激活控制栅极。 在施加触发信号期间，触发信号可能由于电路寄生而降级。 触发信号调节电路可用于从降级的触发信号中去除噪声。 已经由触发信号调节电路调节的触发信号的版本可以被施加到控制门的控制输入。 触发信号调节电路可以包括低通滤波器，迟滞电路和两级缓冲器。 两级缓冲器可以由与环形振荡器回路的反相器中的晶体管具有相同特性的晶体管形成。

公开(公告)号：US07817762B2

公开(公告)日：2010-10-19

申请号：US11299431

申请日：2005-12-12

申请人： Colin Johnstone ,  Eric Breakenridge

发明人： Colin Johnstone ,  Eric Breakenridge

IPC分类号： H04L7/02

CPC分类号： H03K5/1252 ,  H03K5/084 ,  H03K5/1534

摘要： An apparatus and method for detecting leading pulse edges of a signal includes a controller, hysteresis threshold comparators and qualification timers. The controller uses the outputs from the timers in order to determine whether or not a transition of the input signal constitutes a leading pulse edge of the input signal.

摘要翻译： 用于检测信号的引导脉冲沿的装置和方法包括控制器，滞后阈值比较器和限定定时器。 控制器使用来自定时器的输出来确定输入信号的转换是否构成输入信号的前导脉冲沿。

公开(公告)号：US20090189635A1

公开(公告)日：2009-07-30

申请号：US12020727

申请日：2008-01-28

申请人： Roger Allen Booth, JR. ,  John Richard Dangler ,  Matthew Stephen Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur Kanu Patel ,  Paul W. Rudrud

发明人： Roger Allen Booth, JR. ,  John Richard Dangler ,  Matthew Stephen Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur Kanu Patel ,  Paul W. Rudrud

IPC分类号： H03K19/003

CPC分类号： H03K5/084 ,  H03K5/003 ,  H03K5/151

摘要： A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2).

摘要翻译： 一种方法和装置实现了对单端时钟的降低的噪声耦合效应，并且提供了主题电路所在的设计结构。 时钟接收器包括从接收到的输入时钟信号的接收时钟峰值和谷值产生的时钟参考电压。 接收的时钟峰值（VT）和接收时钟谷（VB）被连续采样。 时钟电压基准设置为例如等于VT和VB的平均值; 或（（VT + VB）/ 2）。

公开(公告)号：US20050052309A1

公开(公告)日：2005-03-10

申请号：US10707867

申请日：2004-01-20

申请人： YAO-CHI WANG

发明人： YAO-CHI WANG

IPC分类号： H03K5/003 ,  H03K5/08 ,  H03M1/12 ,  H04L25/06 ,  H04L27/32

CPC分类号： H03K5/003 ,  H03K5/084 ,  H04L25/062

摘要： An automatic threshold voltage control circuit is provided. The circuit comprises a first capacitor, a clock generator, and a switching capacitor network. Wherein the switching capacitor network, receives an analog signal and a plurality of clock signals from the clock generator, where the switching capacitor network stores a portion of charges of the analog signal according to one clock signal, and outputting the portion of charges in according to another clock signal. The portion of charges being associated with the first capacitor generates a threshold voltage. A plurality of sensor control switches is adopted in the present invention in replace of the resistor in the conventional RC filter. Hence, it can be easily integrated into one chip and number of the external devices is reduced, so that hardware costs down. In addition, RC constant can be adjusted by tuning the frequency of the clock signal.

摘要翻译： 提供自动阈值电压控制电路。 电路包括第一电容器，时钟发生器和开关电容器网络。 其中开关电容网络接收来自时钟发生器的模拟信号和多个时钟信号，其中开关电容器网络根据一个时钟信号存储模拟信号的一部分电荷，并根据 另一个时钟信号。 与第一电容器相关联的电荷部分产生阈值电压。 在本发明中采用多个传感器控制开关代替传统RC滤波器中的电阻器。 因此，它可以轻松集成到一个芯片中，并减少了外部设备的数量，从而降低硬件成本。 另外，通过调整时钟信号的频率可以调整RC常数。

公开(公告)号：US06677785B1

公开(公告)日：2004-01-13

申请号：US10202184

申请日：2002-07-24

申请人： Yung-Chow Peng ,  Li-Yueh Wang

发明人： Yung-Chow Peng ,  Li-Yueh Wang

IPC分类号： H03K500

CPC分类号： H03K5/084 ,  G01R19/16547 ,  H03K17/223

摘要： A power level detection circuit detects the voltage level of a power source. The power level detection circuit has a first voltage level detector having an input coupled to the power source and outputting a first signal representative of an upper boundary, a second voltage level detector having an input coupled to the power source and outputting a second signal representative of a desired detection level, and a third voltage level detector having an input coupled to the power source and outputting a third signal representative of a lower boundary. The power level detection circuit also has a control circuit coupled to the first, second and third signals for outputting a power level detection signal if there is a change in the second signal, and when the power level is greater than the level of the third signal and less than the level of the first signal.

摘要翻译： 功率电平检测电路检测电源的电压电平。 功率电平检测电路具有第一电压电平检测器，其具有耦合到电源的输入并输出表示上边界的第一信号，第二电压电平检测器具有耦合到电源的输入端，并输出代表 期望的检测电平，以及具有耦合到电源的输入并输出表示下边界的第三信号的第三电压电平检测器。 功率电平检测电路还具有耦合到第一，第二和第三信号的控制电路，用于在第二信号有变化时输出功率电平检测信号，并且当功率电平大于第三信号的电平时 并且小于第一信号的电平。

公开(公告)号：US06188264B1

公开(公告)日：2001-02-13

申请号：US09443047

申请日：1999-11-18

申请人： Tomoaki Masuta ,  Akira Kakinoki

发明人： Tomoaki Masuta ,  Akira Kakinoki

IPC分类号： H03K508

CPC分类号： H03K5/084

摘要： An automatic threshold level control circuit is provided which is capable of controlling the threshold level without causing the DUTY deterioration. The automatic threshold level control circuit comprises a timing detecting circuit 110a, used for preserving the peak voltage values of each input signals for input signals (ATCIN+ and ATCIN−) and for outputting the preserved voltage values as a reference signal for the threshold level of each input signal, and the automatic threshold level control circuit comprises a pair of peak value detecting circuits PD1 (62) and PD2 (64) for resetting the held voltage values into reference voltages Vref1 and Vref2 by reset signals PD1RST and PD1RST; and the timing detecting circuit 110a for detecting a predetermined timing and outputting the reset signals PD1RST and PD2RST to the peak value detecting circuits PD1 and PD2 for releasing the reset state in accordance with the detected timing.

摘要翻译： 提供一种自动阈值电平控制电路，其能够控制阈值电平而不引起DUTY恶化。自动阈值电平控制电路包括定时检测电路110a，用于保持输入信号的每个输入信号的峰值电压值（ ATCIN +和ATCIN-），并且用于输出保存的电压值作为每个输入信号的阈值电平的参考信号，并且自动阈值电平控制电路包括一对峰值检测电路PD1（62）和PD2（64），用于 通过复位信号PD1RST和PD1RST将保持电压值复位为参考电压Vref1和Vref2; 以及定时检测电路110a，用于检测预定定时，并将复位信号PD1RST和PD2RST输出到峰值检测电路PD1和PD2，以根据检测到的定时解除复位状态。

公开(公告)号：US5381052A

公开(公告)日：1995-01-10

申请号：US88291

申请日：1993-07-06

申请人： Ravindra N. Kolte

发明人： Ravindra N. Kolte

IPC分类号： H03K5/08 ,  H03K5/153

CPC分类号： H03K5/084

摘要： A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal. The input amplifier circuit is also used with slight modification as part of a track-and-hold amplifier. The peak detector circuit works on the principle of counter-balancing the deviation of the input signal from the detected peak value. Thus the advantage of the circuit is that it needs comparatively low gain circuit compared to other approaches. The sample-and-hold or track-and-hold circuit works on the principle of switching the charging current path in a manner similar to a differential amplifier, resulting in very fast switching time.

摘要翻译： 用于光纤接收器的峰值检测器具有电容器，驱动电容器的输入放大器以及耦合在电容器和输入放大器的输入端之间的反馈差分放大器。 输入放大器是互补缓冲器，其单位增益被修改为在一个轨道上包括一个附加晶体管，其接收由差分放大器产生的反相器电压。 逆变器电压等于电容器电压的两倍与施加到峰值检测器的输入电压之间的差值。 正峰值检测器中的输入放大器的功能是使电容器电压在超过逆变器电压时跟踪输入电压，并且等于输入电压小于逆变器电压时的输入电压和逆变器电压的平均值。 负峰值检测器的操作类似但具有相反的极性。 峰值检测器还包含用于在确定复位信号时复位电容器电压的晶体管。 输入放大器电路也被轻微修改，作为跟踪和保持放大器的一部分。 峰值检测电路的工作原理是平衡输入信号与检测到的峰值的偏差。 因此，电路的优点是与其他方法相比，它需要相对较低的增益电路。 采样保持或跟踪和保持电路的工作原理是以类似于差分放大器的方式切换充电电流路径，从而实现非常快的切换时间。

公开(公告)号：US5350950A

公开(公告)日：1994-09-27

申请号：US983736

申请日：1992-12-01

申请人： Naoto Inaba ,  Shinichi Tanaka

发明人： Naoto Inaba ,  Shinichi Tanaka

IPC分类号： H03K5/08 ,  H03K5/153

CPC分类号： H03K5/084

摘要： A binary threshold value setting circuit comprises: a first detecting section to detect the positive polarity side of an input signal, a second detecting section to detect the negative polarity side of the signal; a first envelope detecting section to perform an envelope detection to the signal detected by the first detecting section, a second envelope detecting section to perform an envelope detection to the signal detected by the second detecting section, a threshold value setting section to generate a signal at a level between the level of the signal which has been envelope detected by the first envelope detecting section and the level of the signal which has been envelope detected by the second envelope detecting section, and a capacitor connected between the output side of the first detecting section and the output side of the second detecting section.

摘要翻译： 二值阈值设定电路包括：检测输入信号的正极侧的第一检测部，检测信号的负极侧的第二检测部; 第一包络检测部，对由所述第一检测部检测出的信号进行包络检测;第二包络检测部，对由所述第二检测部检测出的信号进行包络检测;阈值设定部， 由第一包络检测部检测到的包络信号的电平与由第二包络检测部检测出的被包络的信号的电平之间的电平，以及连接在第一检测部的输出侧之间的电容器 和第二检测部分的输出侧。

公开(公告)号：US5015878A

公开(公告)日：1991-05-14

申请号：US426378

申请日：1989-10-25

申请人： Diego Lasagna ,  Francesco P. Mandara

发明人： Diego Lasagna ,  Francesco P. Mandara

IPC分类号： G01P3/481 ,  G01D5/244 ,  G01D5/245 ,  G01R19/175 ,  H03K5/08 ,  H03K5/1536

CPC分类号： G01D5/24476 ,  G01R19/175 ,  H03K5/084 ,  H03K5/1536

摘要： The circuit comprises a first threshold comparator (2,3) with hysteresis which is arranged to provide a reference signal (V.sub.c) indicative of the zero-crossing of the sensor signal (V.sub.p). Also connected to the sensor (P) is an integrator circuit (4) whose output is connected to the input of a second threshold comparator (7). The latter provides an inabling output signal (V.sub.e) only when the integrated signal (V.sub.i) exceeds a reference signal (V.sub.2) whose amplitude varies in a predetermined manner in dependance on the amplitude of the integrated signal (V.sub.i). An inabling circuit (14) is connected to the two threshold comparators (2,3;7) and outputs the signal (V.sub.c) generated by the first comparator (2,3) only when the second comparator (7) emits an enabling output signal (V.sub.e).