An automatic threshold level control circuit is provided which is capable of controlling the threshold level without causing the DUTY deterioration. The automatic threshold level control circuit comprises a timing detecting circuit 110a, used for preserving the peak voltage values of each input signals for input signals (ATCIN+ and ATCIN−) and for outputting the preserved voltage values as a reference signal for the threshold level of each input signal, and the automatic threshold level control circuit comprises a pair of peak value detecting circuits PD1 (62) and PD2 (64) for resetting the held voltage values into reference voltages Vref1 and Vref2 by reset signals PD1RST and PD1RST; and the timing detecting circuit 110a for detecting a predetermined timing and outputting the reset signals PD1RST and PD2RST to the peak value detecting circuits PD1 and PD2 for releasing the reset state in accordance with the detected timing.