公开(公告)号：US20070206685A1

公开(公告)日：2007-09-06

申请号：US11653421

申请日：2007-01-16

Applicant: Masaki Mori ,  Tadatoshi Asada ,  Susumu Ueda ,  Hirokazu Toyoda

Inventor： Masaki Mori ,  Tadatoshi Asada ,  Susumu Ueda ,  Hirokazu Toyoda

IPC: H04L25/00

CPC classification number: H04L25/085 ,  H03K4/94 ,  H03K5/1252 ,  H03K17/04113 ,  H04L25/0286 ,  H04L25/10

Abstract: A noise free transceiver circuit includes a communication line, a power source line, a ground line, an output transistor having output terminals connected between the communication line and the ground line for outputting a communication signal to the communication line, a first circuit for applying a trapezoidal signal to the input terminal of the output transistor to turn on in synchronism with a transmission signal and a second circuit for turning off the output transistor when the level of the transmission signal is high. The output transistor is turned off when the communication signal is outputted. Therefore, noises of the power line are shut out of the output transistor.

Abstract translation: 无噪声收发电路包括通信线路，电源线路，接地线路，输出端子连接在通信线路和接地线路之间的输出晶体管，用于向通信线路输出通信信号;第一电路， 梯形信号输出到输出晶体管的输入端以与传输信号同步地接通，以及第二电路，用于当传输信号的电平为高时关断输出晶体管。 当输出通信信号时，输出晶体管截止。 因此，输出晶体管的电源线的噪声被关闭。

公开(公告)号：US07005901B1

公开(公告)日：2006-02-28

申请号：US10927709

申请日：2004-08-27

Applicant: Yi Jiang ,  Raed Moughabghab

Inventor： Yi Jiang ,  Raed Moughabghab

IPC: H03K4/94

CPC classification number: H03K4/94 ,  H03K4/023

Abstract: A process, temperature and supply insensitive trapezoidal pulse generator includes a stable reference current source for generating a stable reference current. The trapezoidal pulse generator includes a current amplification circuit adapted to receive the stable reference current and operable responsive to the stable reference current to amplify the stable reference current to a mirrored current. The trapezoidal pulse generator includes an output circuit coupled to the current amplification circuit and adapted to receive the mirrored current and operable in a second frequency to generate a trapezoidal pulse.

Abstract translation: 过程，温度和电源不灵敏梯形脉冲发生器包括用于产生稳定参考电流的稳定参考电流源。 梯形脉冲发生器包括电流放大电路，其适于接收稳定的参考电流，并且响应稳定的参考电流可操作以将稳定的参考电流放大到镜像电流。 梯形脉冲发生器包括耦合到电流放大电路的输出电路，并适于接收镜像电流并以第二频率操作以产生梯形脉冲。

公开(公告)号：US06747504B2

公开(公告)日：2004-06-08

申请号：US10223282

申请日：2002-08-19

Applicant: Richard D. Simpson ,  Jonathan P. Milton ,  Simon D. Forey

Inventor： Richard D. Simpson ,  Jonathan P. Milton ,  Simon D. Forey

IPC: H03K1728

CPC classification number: H03K4/94 ,  H03K5/13 ,  H03K17/164 ,  H03K19/00361

Abstract: A control slew rate output driver has a plurality of component drivers that are switched on in turn to provide an edge on the output. A control circuit provides a series of respective control signals component drivers, which are correspondingly switched on in turn. The control circuit takes a signal, preferably a data signal, and supplies it in parallel to a plurality of delay buffers, which delay the data signal by different amounts to produce the control signals for the component drivers. The delay buffers are voltage controlled and the control voltage for each is provided by a respective tap of a voltage divider. The current passes through the voltage divider can be changed to change the control voltages and, hence, the overall rise or fall time provided by the output driver.

Abstract translation: 控制转换速率输出驱动器具有多个组件驱动器，其依次接通以在输出端提供边缘。 控制电路提供一系列相应的控制信号分量驱动器，其相应地依次接通。 控制电路采取信号，优选地是数据信号，并且将其并行地提供给多个延迟缓冲器，这些延迟缓冲器将数据信号延迟不同的量，以产生用于部件驱动器的控制信号。 延迟缓冲器是电压控制的，并且每个的控制电压由分压器的相应抽头提供。 可以改变通过分压器的电流来改变控制电压，从而改变由输出驱动器提供的整体上升或下降时间。

公开(公告)号：US20030117197A1

公开(公告)日：2003-06-26

申请号：US10223282

申请日：2002-08-19

Inventor： Richard D. Simpson ,  Jonathan P. Milton ,  Simon D. Forey

IPC: H03K005/12

CPC classification number: H03K4/94 ,  H03K5/13 ,  H03K17/164 ,  H03K19/00361

Abstract: A control slew rate output driver has a plurality of component drivers that are switched on in turn to provide an edge on the output. A control circuit provides a series of respective control signals component drivers, which are correspondingly switched on in turn. The control circuit takes a signal, preferably a data signal, and supplies it, in parallel to a plurality of delay buffers, which delay the data signal by different amounts to produce the control signals for the component drivers. The delay buffers are voltage controlled and the control voltage for each is provided by a respective tap of a voltage divider. The current passes through the voltage divider can be changed to change the control voltages and, hence, the overall rise or fall time provided by the output driver.

Abstract translation: 控制转换速率输出驱动器具有多个组件驱动器，其依次接通以在输出端提供边缘。 控制电路提供一系列相应的控制信号分量驱动器，其相应地依次接通。 控制电路采取一个信号，最好是一个数据信号，并且并行地提供给多个延迟缓冲器，这些延迟缓冲器将数据信号延迟不同的量，以产生组件驱动器的控制信号。 延迟缓冲器是电压控制的，并且每个的控制电压由分压器的相应抽头提供。 可以改变通过分压器的电流来改变控制电压，从而改变由输出驱动器提供的整体上升或下降时间。

公开(公告)号：US20020140465A1

公开(公告)日：2002-10-03

申请号：US10052981

申请日：2001-11-08

Inventor： Junichi Nagata ,  Akio Kojima

IPC: H03K004/94

CPC classification number: H03K17/16 ,  H03K4/94 ,  H03K17/04126 ,  H03K2217/0036

Abstract: The present invention discloses an output circuit, by which it is possible to reduce power consumption while maintaining maximum voltage value to be outputted at high level. In this output circuit, a charge-and-discharge circuit uses a terminal voltage Vc of a capacitor as a trapezoidal wave voltage, and a drive circuit drives an output transistor based on the terminal voltage Vc, and a voltage Vo equal to the terminal voltage Vc is outputted to the load. A voltage detection circuit detects an emitter voltage (VcnullVF) of the transistor and generates an electric current proportional to the terminal voltage Vc. This electric current is turned to a base current of the output transistor via a variable current circuit. Therefore, a base current proportional to the output voltage Vo is supplied to the output transistor.

Abstract translation: 本发明公开了一种输出电路，通过该输出电路可以在保持最高电压值以高电平输出的同时降低功耗。 在该输出电路中，充放电电路使用电容器的端子电压Vc作为梯形波电压，驱动电路基于端子电压Vc驱动输出晶体管，并且将电压Vo等于端子电压 Vc被输出到负载。 电压检测电路检测晶体管的发射极电压（Vc + VF），并产生与端子电压Vc成比例的电流。 该电流通过可变电流电路转换为输出晶体管的基极电流。 因此，与输出电压Vo成比例的基极电流被提供给输出晶体管。

公开(公告)号：US5929671A

公开(公告)日：1999-07-27

申请号：US596463

申请日：1996-02-05

Applicant: Scott C. Best

Inventor： Scott C. Best

IPC: H03K4/94 ,  H03K17/041 ,  H03K4/06

CPC classification number: H03K4/94 ,  H03K17/04113

Abstract: A novel waveform generating for generating a waveform having symmetrical rise and fall times. The waveform generator of the present invention includes a first current source, a second current source, a MOS capacitor and a clamping circuit. The first current source and the second current source are coupled to a node such that current generated by the first current source flows into the capacitor and current generated by the second current source flows out of the capacitor. The clamping circuit is also coupled to the node such that the output voltage generated by the waveform generator is limited to a minimum and a maximum value. Therefore, by controlling the current flowing into the node, and the capacitance at the node, the rate at which the output voltage changes over time is controlled. As such, a waveform having very precise rise and fall times is generated.

Abstract translation: 一种用于产生具有对称上升和下降时间的波形的新颖波形。 本发明的波形发生器包括第一电流源，第二电流源，MOS电容器和钳位电路。 第一电流源和第二电流源耦合到节点，使得由第一电流源产生的电流流入电容器，并且由第二电流源产生的电流流出电容器。 钳位电路还耦合到节点，使得由波形发生器产生的输出电压被限制到最小值和最大值。 因此，通过控制流入节点的电流和节点处的电容，控制输出电压随时间变化的速率。 因此，产生具有非常精确的上升和下降时间的波形。

公开(公告)号：US5355390A

公开(公告)日：1994-10-11

申请号：US700698

申请日：1991-05-16

Applicant: Kiyoshi Yamamoto ,  Yoshihisa Sato ,  Satoshi Suzuki ,  Masayuki Kobayashi

Inventor： Kiyoshi Yamamoto ,  Yoshihisa Sato ,  Satoshi Suzuki ,  Masayuki Kobayashi

IPC: H04B15/00 ,  H03K4/94 ,  H03K17/66 ,  H04L5/00 ,  H04L25/02 ,  H04L25/08 ,  H04B3/00

CPC classification number: H04L25/0286 ,  H03K17/66 ,  H03K4/94 ,  H04L25/0274 ,  H04L25/0292

Abstract: A transmitting circuit is provided which includes a control circuit for transmitting and receiving a communication signal. Transmit information is modulated into a trapezoidal wave signal using a waveform shaping circuit. A communication signal is first generated on the basis of the trapezoidal wave signal and transmitted to a first transmission line. From this communication signal, a second communication signal is generated having an inverted polarity waveform shape relative to the first communication signal. This inverted polarity triangular wave signal is, in turn, output from a second transmission line BUS-. In addition, a receiving circuit is provided for receiving like signals from other communication devices which share the first and second transmission lines BUS+ and BUS-. The receiving circuit includes a comparator circuit for demodulating received signals on the transmission lines to generate square wave equivalent signals which a processing unit can logically interpret. Because communication signals are transmitted (received) and derived in the described manner, they are not subject to adverse effects, such as can result from fluctuation of GND potential levels and power supply differences amongst remote communication systems. Furthermore, because an inverted triangular waveform is generated in addition to, and on the basis of, a regular, modulated triangular wave signal, phase shift problems are avoided and radiation of harmonics noise is favorably reduced even at intermediate, or higher, transmission rates.

Abstract translation: 提供一种发送电路，其包括用于发送和接收通信信号的控制电路。 使用波形整形电路将发送信息调制成梯形波信号。 首先根据梯形波信号生成通信信号，并将其发送到第一传输线。 从该通信信号，产生具有相对于第一通信信号的反极性波形形状的第二通信信号。 反转的极性三角波信号又从第二传输线BUS-输出。 此外，提供接收电路用于接收来自共享第一和第二传输线BUS +和BUS-的其它通信设备的类似信号。 接收电路包括用于解调传输线上的接收信号的比较器电路，以产生处理单元可逻辑解释的方波等效信号。 由于以所述方式发送（接收）和导出通信信号，所以它们不会受到不利影响，例如可能由远程通信系统之间的GND电位波动和电源差异引起。 此外，由于除了规则的调制三角波信号之外并且基于规则的调制三角波信号产生倒三角波形，避免了相移问题，甚至在中间或更高的传输速率下也有利地降低了谐波噪声的辐射。

公开(公告)号：US5070256A

公开(公告)日：1991-12-03

申请号：US403900

申请日：1989-09-01

Applicant: David S. Grondalski

Inventor： David S. Grondalski

IPC: H03K4/94 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0948

CPC classification number: H03K19/0948 ,  H03K17/163 ,  H03K19/00361 ,  H03K4/94

Abstract: A transmitter circuit for transmitting a digital data signal over a bus in a digital data processing system includes a MOSFET bus driver transistor having a gate to drain capacitance C.sub.GD which substantially dominates other capacitances at the gate terminal. The bus driver transistor is driven by a buffer circuit having pull-up and pull-down transistors current through which is controlled by current sources. The gate terminal of the driver transistor is connected to, and controlled by, the node between the pull-up and pull-down transistors. The drain terminal of the driver transistor is connected to, and controls, a bus line. To assert a signal on the bus line, the pull-up transistor is turned on to drive current into the node at a rate governed by the current source, which increases the voltage level of the node. When the voltage level of the node reaches the driver transistor's threshold level, the driver transistor begins to turn on, allowing the voltage level of the bus line to drop. Contemporaneously, current flows into the node from the bus line through the driver transistor's high gate to drain capacitance, thereby limiting the voltage level of the node, and thus the current flow through the driver transistor. Thus, current flows through the driver transistor from the bus line in a manner controlled, in part, by the voltage level on the bus line. In negating a signal on the bus line, the operations are similar, with current flowing out of the node through the pull-down transistor and the driver transistor's gate to drain capacitance.

Abstract translation: 用于在数字数据处理系统中通过总线发送数字数据信号的发送器电路包括具有栅极 - 漏极电容CGD的MOSFET总线驱动晶体管，其基本上支配栅极端子处的其它电容。 总线驱动晶体管由具有由电流源控制的上拉和下拉晶体管电流的缓冲电路驱动。 驱动晶体管的栅极端子连接到并由上拉和下拉晶体管之间的节点控制。 驱动晶体管的漏极端子与母线相连接并控制。 为了在总线上断言一个信号，上拉晶体管导通，以电流源控制的速率驱动电流进入节点，这增加了节点的电压电平。 当节点的电压电平达到驱动晶体管的阈值电平时，驱动晶体管开始导通，允许总线线路的电压下降。 同时，电流从总线通过驱动晶体管的高栅极流入节点，从而限制节点的电压电平，从而限制电流通过驱动晶体管。 因此，电流以总线线路上的电压电平部分控制的方式从总线流过驱动晶体管。 在否定总线上的信号时，操作类似，电流通过下拉晶体管和驱动晶体管的栅极流出节点以漏电容。

公开(公告)号：US5023473A

公开(公告)日：1991-06-11

申请号：US593375

申请日：1990-10-01

Applicant: Takashi Toyooka ,  Yoji Maruyama ,  Ryo Suzuki

Inventor： Takashi Toyooka ,  Yoji Maruyama ,  Ryo Suzuki

IPC: G11C11/14 ,  G11C19/08 ,  H03K4/06 ,  H03K4/94

CPC classification number: G11C19/085 ,  H03K4/06 ,  H03K4/94

Abstract: This invention accomplishes low power consumption by a drive circuit for a Bloch line memory, which includes a power source, a bias magnetic field coil, a plurality of switching means and means for returning the power supplied to the bias magnetic field to the power source. The present invention can set the waveform of a pulse current (coil current) to a desired waveform by particularly using a transformer, and can improve the transfer characteristics of the Both line pair.

Abstract translation: 本发明通过用于Bloch线路存储器的驱动电路实现低功耗，其包括电源，偏置磁场线圈，多个开关装置和用于将供应到偏置磁场的电力返回到电源的装置。 本发明可以通过特别使用变压器将脉冲电流（线圈电流）的波形设定为期望的波形，并且可以提高双线对的传输特性。

公开(公告)号：US5003195A

公开(公告)日：1991-03-26

申请号：US322489

申请日：1989-03-10

Applicant: Desi Stelling ,  Robert J. Aleksa ,  Nicholas J. Wilt

Inventor： Desi Stelling ,  Robert J. Aleksa ,  Nicholas J. Wilt

IPC: H03K4/94 ,  H03K17/66

CPC classification number: H03K17/66 ,  H03K4/94

Abstract: A capacitor is charged and discharged through switch selectable resistors from regulated DC voltage supplies and clamping diodes to provide the bias signal to control the rise and fall times of the RF output pulse of a PIN diode attenuator. An isolation buffer isolates charging and discharging transients from the bias signal. An adjustable AC gain and adjustable DC offset inverting amplifier provides the isolation buffered signal to a high impedance, very low output AC impedance source for driving the bias input of the PIN diode attenuator. The DC offset is provided by an adjustable regulated voltage source coupled to the inverting amplifier.

Abstract translation: 电容器通过可调节的直流电压源和钳位二极管的开关选择电阻进行充电和放电，以提供偏置信号来控制PIN二极管衰减器的RF输出脉冲的上升和下降时间。 隔离缓冲器隔离偏置信号的充电和放电瞬变。 可调的交流增益和可调直流偏移反相放大器将隔离缓冲信号提供给高阻抗，非常低的输出AC阻抗源，用于驱动PIN二极管衰减器的偏置输入。 DC偏移由耦合到反相放大器的可调节稳压电源提供。