公开(公告)号：US20140092692A1

公开(公告)日：2014-04-03

申请号：US13630278

申请日：2012-09-28

Applicant: Wanfang Tsai

Inventor： Wanfang Tsai

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C7/1036 ,  G11C7/1087 ,  G11C2207/107

Abstract: A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.

Abstract translation: 提出了可用于固定或可变速率串行到并行数据转换的移位寄存器结构。 在1到N转换中，在传输到（N×m）范围的并行数据总线之前，数据从m位串行数据总线接收并被加载到N宽m锁存器中。 基于关于N m位宽数据单元如何被忽略的信息，数据将以可变速率被输出。 当将数据从串行总线加载到锁存器中时，刷新时，当前数据被加载到锁存器的所有N个单元中，每个随后的时钟加载少一个锁存器。 当并行总线上的单元的内容被忽略时，该单元与前一个单元同时关闭，以便留下冗余数据。

公开(公告)号：US08625345B2

公开(公告)日：2014-01-07

申请号：US13191836

申请日：2011-07-27

Applicant: Nicholas Hendrickson

Inventor： Nicholas Hendrickson

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

Abstract: Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.

Abstract translation: 公开了操作存储器件的装置和方法。 在一种这样的方法中，存储器单元的数据状态的第一部分被确定并从存储器件传送，同时继续确定相同存储器单元的数据状态的剩余部分。 在至少一种方法中，在第一感测阶段期间确定存储器单元的数据状态，并且在存储器单元经历额外的检测相位时传送，以确定存储器单元的数据状态的附加部分。

公开(公告)号：US20130179619A1

公开(公告)日：2013-07-11

申请号：US13785133

申请日：2013-03-05

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G06F13/40

CPC classification number: G11C7/1036 ,  G01R31/318572 ,  G06F3/0601 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/4291 ,  G11C7/1066 ,  H04L29/08549 ,  H04L67/1097

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract translation: 双引脚通信接口总线和控制电路与集成电路中的电路板，集成电路或嵌入式核心一起使用。 一个引脚将数据双向传输，并将地址和指令信息从控制器传送到所选端口。 另一个引脚将时钟信号从控制器传送到所需电路或电路中或其上的目标端口或端口。 总线可用于串行访问电路，其中IC上的引脚或芯上的端子的可用性最小。 总线用于通信，例如与IC或核心设计的功能操作有关的串行通信，或与IC或核心设计的测试，仿真，调试和/或跟踪操作相关的串行通信。

公开(公告)号：US08130562B2

公开(公告)日：2012-03-06

申请号：US12692111

申请日：2010-01-22

Applicant: Daichi Kaku ,  Toshimasa Namekawa

Inventor： Daichi Kaku ,  Toshimasa Namekawa

IPC: G11C7/10

CPC classification number: G11C7/1036 ,  G11C8/04 ,  G11C19/28 ,  G11C19/287

Abstract: A semiconductor memory device includes n stages of memory cell units, sense amplifier units, and shift registers. N units of the shift registers are connected to one another on the left end sides. The signal processing units and the reversed signal processing units are disposed adjacent to one another in each of the n units of the shift registers. The signal processing units located on the odd-numbered positions counted from the input end side are connected to one another. The reversed signal processing units located on the even-numbered positions counted from the input end side are connected to one another. The signal processing units located on the end opposite to the input end side are connected to the reversed signal processing units located on the end opposite to the input end side. Each of the signal processing units includes the logic circuit unit and the flip-flop while each of the reversed signal processing units includes the reversed logic circuit unit and the reversed flip-flop.

Abstract translation: 半导体存储器件包括n级存储单元，读出放大器单元和移位寄存器。 移位寄存器的N个单元在左端相互连接。 信号处理单元和反向信号处理单元在移位寄存器的n个单元中的每一个中彼此相邻地布置。 位于从输入端侧计数的奇数位置的信号处理单元彼此连接。 位于从输入端侧计数的偶数位置的反转信号处理单元彼此连接。 位于与输入端侧相反的端部的信号处理单元连接到位于与输入端侧相对的端部的反转信号处理单元。 每个信号处理单元包括逻辑电路单元和触发器，而每个反向信号处理单元包括反向逻辑电路单元和反向触发器。

公开(公告)号：US20110205795A1

公开(公告)日：2011-08-25

申请号：US13029892

申请日：2011-02-17

Applicant: Toshiki Rai ,  Sadao Yoshikawa

Inventor： Toshiki Rai ,  Sadao Yoshikawa

IPC: G11C16/08

CPC classification number: G11C7/1036 ,  G11C7/08

Abstract: With a serial interface memory device of this invention, a read-out rate of data is increased, while an increase in a size of a circuit is suppressed. An EEPROM is provided with a memory cell array storing data, a row address decoder and a column address decoder that select an address of the memory cell array in accordance with an address signal serially inputted in synchronization with a clock, sense amplifiers SA0-SA5, SA_M0 and SA_M1 each provided corresponding to each bit of the data, and a shift register that outputs the data read out from the sense amplifiers serially from a first bit. The column address decoder commences reading out two candidate data for the first bit by inputting each of the two candidate data to each of the two sense amplifiers SA_M0 and SA_M1, respectively, before all bits of the column address signal are established.

Abstract translation: 利用本发明的串行接口存储器件，增加了数据的读出速率，同时抑制了电路尺寸的增加。 EEPROM具有存储数据的存储单元阵列，行地址解码器和列地址解码器，其根据与时钟同步串行输入的地址信号选择存储单元阵列的地址，读出放大器SA0-SA5， SA_M0和SA_M1各自对应于数据的每个位，以及移位寄存器，其从第一位序列地输出从读出放大器读出的数据。 在列地址信号的所有位建立之前，列地址解码器分别将两个候选数据中的每一个输入到两个读出放大器SA_M0和SA_M1中的每一个上，分别读出第一位的两个候选数据。

公开(公告)号：US20100195410A1

公开(公告)日：2010-08-05

申请号：US12692111

申请日：2010-01-22

Applicant: Daichi KAKU ,  Toshimasa Namekawa

Inventor： Daichi KAKU ,  Toshimasa Namekawa

IPC: G11C7/10 ,  G11C7/00 ,  G11C8/18

CPC classification number: G11C7/1036 ,  G11C8/04 ,  G11C19/28 ,  G11C19/287

Abstract: A semiconductor memory device includes n stages of memory cell units, sense amplifier units, and shift registers. N units of the shift registers are connected to one another on the left end sides. The signal processing units and the reversed signal processing units are disposed adjacent to one another in each of the n units of the shift registers. The signal processing units located on the odd-numbered positions counted from the input end side are connected to one another. The reversed signal processing units located on the even-numbered positions counted from the input end side are connected to one another. The signal processing units located on the end opposite to the input end side are connected to the reversed signal processing units located on the end opposite to the input end side. Each of the signal processing units includes the logic circuit unit and the flip-flop while each of the reversed signal processing units includes the reversed logic circuit unit and the reversed flip-flop.

Abstract translation: 半导体存储器件包括n级存储单元，读出放大器单元和移位寄存器。 移位寄存器的N个单元在左端相互连接。 信号处理单元和反向信号处理单元在移位寄存器的n个单元中的每一个中彼此相邻地布置。 位于从输入端侧计数的奇数位置的信号处理单元彼此连接。 位于从输入端侧计数的偶数位置的反转信号处理单元彼此连接。 位于与输入端侧相反的端部的信号处理单元连接到位于与输入端侧相对的端部的反转信号处理单元。 每个信号处理单元包括逻辑电路单元和触发器，而每个反向信号处理单元包括反向逻辑电路单元和反向触发器。

公开(公告)号：US07768841B2

公开(公告)日：2010-08-03

申请号：US12478133

申请日：2009-06-04

Applicant: Raul-Adrian Cernea

Inventor： Raul-Adrian Cernea

IPC: G11C11/00

CPC classification number: G11C16/06 ,  G11C7/1036 ,  G11C7/1051 ,  G11C19/00 ,  G11C19/28

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

Abstract translation: 选择存储器单元阵列的电路用于保持存储单元的读取数据或写入数据。 存储单元可以是多状态存储器单元。 有一个移位寄存器链，具有数组列的阶段。 选通脉冲通过该移位寄存器移位。 每个时钟的选通点依次处于并使能不同的选择电路。 那个已经被选通使能的特定选择电路然后将执行一定的功能。 在读取模式下，所选择的选择电路将存储的信息发送到输出缓冲器，以从集成电路输出。 而在编程模式下，所选择的选择电路将从输入缓冲器接收数据。 该数据将被写入存储单元。

公开(公告)号：US20080253203A1

公开(公告)日：2008-10-16

申请号：US12047793

申请日：2008-03-13

Applicant: Ji Hyae Bae

Inventor： Ji Hyae Bae

IPC: G11C7/00 ,  G11C8/18

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C7/106

Abstract: A data output circuit for a semiconductor memory apparatus includes a data output control unit that generates a selection signal, an output timing signal, and an input control signal in response to a read command and a clock, and a signal-responsive data output unit that receives parallel data in response to the input control signal, arranges the parallel data in response to the selection signal, and sequentially outputs the arranged parallel data as serial data in synchronization with the output timing signal.

Abstract translation: 一种用于半导体存储装置的数据输出电路，包括：数据输出控制单元，响应读取命令和时钟，产生选择信号，输出定时信号和输入控制信号;以及信号响应数据输出单元， 响应于输入控制信号接收并行数据，根据选择信号排列并行数据，并且与输出定时信号同步地顺序输出排列的并行数据作为串行数据。

公开(公告)号：US20070241369A1

公开(公告)日：2007-10-18

申请号：US11405762

申请日：2006-04-18

Applicant: Akira Goda ,  Seiichi Aritome

Inventor： Akira Goda ,  Seiichi Aritome

IPC: H01L27/10

CPC classification number: G11C7/02 ,  G11C7/1036 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

Abstract: Methods and apparatus are provided. In one embodiment, a memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The first bit line is formed at a first vertical layer and is coupled to a first source/drain region of the first multiplexer gate. The input of the sensing device is formed at a second vertical layer different than the first vertical layer and is coupled to a second source/drain region of the first multiplexer gate and a first source/drain region of the second multiplexer gate. The second bit line is formed at the first vertical layer and is coupled to a second source/drain region of the second multiplexer gate.

Abstract translation: 提供了方法和装置。 在一个实施例中，存储器件包括通过第一多路复用器门选择性地耦合到感测器件的输入的第一位线，以及通过第二多路复用器门选择性地耦合到感测器件的输入的第二位线。 第一位线形成在第一垂直层并且耦合到第一多路复用器门的第一源/漏区。 感测装置的输入形成在不同于第一垂直层的第二垂直层上，并且耦合到第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第一源极/漏极区域。 第二位线形成在第一垂直层处，并且耦合到第二多路复用器门的第二源极/漏极区域。

公开(公告)号：US20060123306A1

公开(公告)日：2006-06-08

申请号：US11258315

申请日：2005-10-25

Applicant: Lee Whetsel

Inventor： Lee Whetsel

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G11C7/1036 ,  G01R31/318572 ,  G06F3/0601 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/4291 ,  G11C7/1066 ,  H04L29/08549

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract translation: 双引脚通信接口总线和控制电路与集成电路中的电路板，集成电路或嵌入式核心一起使用。 一个引脚将数据双向传输，并将地址和指令信息从控制器传送到所选端口。 另一个引脚将时钟信号从控制器传送到所需电路或电路中或其上的目标端口或端口。 总线可用于串行访问电路，其中IC上的引脚或芯上的端子的可用性最小。 总线用于通信，例如与IC或核心设计的功能操作有关的串行通信，或与IC或核心设计的测试，仿真，调试和/或跟踪操作相关的串行通信。