公开(公告)号：US20090316483A1

公开(公告)日：2009-12-24

申请号：US12457416

申请日：2009-06-10

Applicant: Jong-Hwa Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

Inventor： Jong-Hwa Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3468 ,  G11C16/3486 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/00

Abstract: The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash memory device to be invalid, according to whether a loop number of the programmed page is out of a reference loop range.

Abstract translation: 本发明提供一种包括闪速存储器件的存储器系统的操作方法。 该方法包括对闪速存储器件的所选存储块中包括的至少一个页面进行编程; 以及根据编程页面的循环编号是否超出参考循环范围，确定所选择的存储器块或闪存器件无效。

公开(公告)号：US07606074B2

公开(公告)日：2009-10-20

申请号：US12242831

申请日：2008-09-30

Applicant: Jun Wan ,  Jeffrey W Lutze ,  Chan-Sui Pang

Inventor： Jun Wan ,  Jeffrey W Lutze ,  Chan-Sui Pang

IPC: G11C11/34

CPC classification number: G11C8/08 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3468

Abstract: Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.

Abstract translation: 在擦除操作期间，补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。 补偿电压可以补偿与其他存储器单元和/或选择栅极的NAND串的存储器单元电容耦合的电压。 补偿电压可以施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。 可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。 还可以将补偿电压施加到内部存储器单元，以使其与端部存储器单元的擦除行为相等。 此外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。 可以使用各种补偿电压。

公开(公告)号：US20090231924A1

公开(公告)日：2009-09-17

申请号：US12467348

申请日：2009-05-18

Applicant: Michio NAKAGAWA ,  Koji Sakui

Inventor： Michio NAKAGAWA ,  Koji Sakui

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C16/3468

Abstract: A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals. Further, the circuit for applying said plurality of pulse signals includes a first circuit for generating a first clock having a first amplitude voltage and a second clock having a second amplitude voltage which is higher than said first amplitude voltage, a second circuit for generating said plurality of said pulse signal having corresponding predetermined voltages based on said first clock or said second clock input from said first circuit respectively, and a third circuit for stopping an input of said first clock and said second clock to said second circuit when said plurality of pulse signals generated by said second circuit reach said corresponding predetermined voltages respectively.

Abstract translation: 非易失性半导体存储器件包括多个电可重编程存储器单元，用于将具有对应的高电位电位的多个脉冲信号逐步增加到所述存储单元的电路，以及用于检测所述存储单元的阈值之后的检验电路 应用所述多个脉冲信号。 此外，用于施加所述多个脉冲信号的电路包括用于产生具有第一幅度电压的第一时钟的第一电路和具有高于所述第一幅度电压的第二幅度电压的第二时钟，用于产生所述多个脉冲信号的第二电路 分别基于所述第一时钟或从所述第一电路输入的所述第二时钟的所述脉冲信号具有相应的预定电压;以及第三电路，用于当所述多个脉冲信号时停止所述第一时钟和所述第二时钟的输入到所述第二电路 所述第二电路产生的电压分别达到相应的预定电压。

公开(公告)号：US07561476B2

公开(公告)日：2009-07-14

申请号：US11072198

申请日：2005-03-03

Applicant: Kiyoshi Kato

Inventor： Kiyoshi Kato

IPC: G11C16/04

CPC classification number: G11C16/3472 ,  G11C16/3468 ,  G11C16/3481

Abstract: Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier (102) that performs reading is connected to a switch which switches an operation voltage applied to a memory cell in accordance with a verify signal Sv, and the verify operation is finished concurrently with having the verify signal Sv switched. By obtaining such circuit construction and simultaneously performing writing/erasing and reading, it becomes possible to perform high-speed verify writing/erasing.

公开(公告)号：US07499338B2

公开(公告)日：2009-03-03

申请号：US11549553

申请日：2006-10-13

Applicant: Fumitoshi Ito

Inventor： Fumitoshi Ito

IPC: G11C11/34

CPC classification number: G11C16/3468 ,  G11C16/3477

Abstract: Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of memory cells closer to a verify level for the erased state. A set of memory cells can be soft programmed by soft programming portions of the set to provide more consistent soft programming rates and threshold voltages. A first soft programming pulse can be applied to a first group of cells of the set while inhibiting soft programming of a second group of cells. A second soft programming pulse can then be applied to the second group of cells while inhibiting soft programming of the first group of cells. A small positive voltage of lower magnitude than the soft programming pulses can be applied to the group of cells to be inhibited. The size of the small positive voltage can be chosen so that each memory cell of the set will experience similar capacitive coupling effects from neighboring transistors when it is undergoing soft programming.

Abstract translation: 执行软编程以缩小一组擦除的存储器单元的阈值电压分布。 软编程可以将存储器单元的阈值电压更接近擦除状态的验证电平。 一组存储器单元可以由该组的软编程部分进行软编程，以提供更一致的软编程速率和阈值电压。 第一软编程脉冲可以被应用于组的第一组单元，同时抑制第二组单元的软编程。 然后可以将第二软编程脉冲施加到第二组单元，同时抑制第一组单元的软编程。 与软编程脉冲相比，较小幅度的正电压可以施加到待抑制的电池组上。 可以选择小正电压的大小，使得当其正在进行软编程时，该组的每个存储单元将经历来自相邻晶体管的类似的电容耦合效应。

公开(公告)号：US20090021983A1

公开(公告)日：2009-01-22

申请号：US12242831

申请日：2008-09-30

Applicant: Jun Wan ,  Jeffrey W. Lutze ,  Chan-Sui Pang

Inventor： Jun Wan ,  Jeffrey W. Lutze ,  Chan-Sui Pang

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C8/08 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3468

Abstract: Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.

Abstract translation: 在擦除操作期间，补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。 补偿电压可以补偿与其他存储器单元和/或选择栅极的NAND串的存储器单元电容耦合的电压。 补偿电压可以施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。 可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。 还可以将补偿电压施加到内部存储器单元，以将其擦除行为与端部存储器单元相等。 此外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。 可以使用各种补偿电压。

公开(公告)号：US07463532B2

公开(公告)日：2008-12-09

申请号：US11316119

申请日：2005-12-21

Applicant: Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

Inventor： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

IPC: G11C11/34

CPC classification number: G11C16/3468

Abstract: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

Abstract translation: 根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。 在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。 例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。 如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。 通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。 例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。 这样的字符串可能是有缺陷的，并被映射出存储器件。

公开(公告)号：US07450433B2

公开(公告)日：2008-11-11

申请号：US11025620

申请日：2004-12-29

Applicant: Jun Wan ,  Jeffrey W. Lutze ,  Chan-Sui Pang

Inventor： Jun Wan ,  Jeffrey W. Lutze ,  Chan-Sui Pang

IPC: G11C11/34

CPC classification number: G11C8/08 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3468

Abstract: Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.

Abstract translation: 在擦除操作期间，补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。 补偿电压可以补偿与其他存储器单元和/或选择栅极的NAND串的存储器单元电容耦合的电压。 补偿电压可以施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。 可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。 还可以将补偿电压施加到内部存储器单元，以使其与端部存储器单元的擦除行为相等。 此外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。 可以使用各种补偿电压。

公开(公告)号：US07411825B2

公开(公告)日：2008-08-12

申请号：US11450355

申请日：2006-06-12

Applicant: Hiroyuki Kutsukake ,  Fumitaka Arai

Inventor： Hiroyuki Kutsukake ,  Fumitaka Arai

IPC: G11C16/04

CPC classification number: G11C16/3468 ,  G11C16/0483

Abstract: A semiconductor integrated circuit device includes first to third memory cell units, first and second bit lines, and first and second source lines. The first to third memory cell units include memory cell transistors serially connected between selection transistors. The first bit line is commonly connected to one end of the current path of the first memory cell unit and one end of the current path of the second memory cell unit. The second bit line is connected to one end of the current path of the third memory cell unit. The first source line is connected to the other end of the current path of the first memory cell unit. The second source line is commonly connected to the other end of the current path of the second memory cell unit and the other end of the current path of the third memory cell unit.

Abstract translation: 半导体集成电路器件包括第一至第三存储单元单元，第一和第二位线以及第一和第二源极线。 第一至第三存储单元单元包括串联连接在选择晶体管之间的存储单元晶体管。 第一位线通常连接到第一存储单元单元的当前路径的一端和第二存储单元单元的当前路径的一端。 第二位线连接到第三存储单元单元的当前路径的一端。 第一源极线连接到第一存储单元单元的当前路径的另一端。 第二源极线通常连接到第二存储单元单元的当前路径的另一端和第三存储单元单元的当前路径的另一端。

公开(公告)号：US07408804B2

公开(公告)日：2008-08-05

申请号：US11296071

申请日：2005-12-06

Applicant: Gerrit Jan Hemink ,  Teruhiko Kamei

Inventor： Gerrit Jan Hemink ,  Teruhiko Kamei

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3468 ,  G11C16/3472 ,  G11C16/3477 ,  G11C2211/5621 ,  G11C2216/18

Abstract: A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.

Abstract translation: 一组非易失性存储元件被划分为用于软编程的子集，以便更软地编程较慢的软编程元件。 整个元素组被软编程，直到被验证为软编程（或直到第一个元素子集被验证为软编程，而不是第二个子集验证）。 在集合被验证为软编程之后，元素的第一子集被禁止进一步的软编程，而在第二子元素上执行附加的软编程。 第二子集可以包括较慢的软编程元素。 然后可以将第二个子集进行软编程验证，同时将第一个子集排除在验证之外。 软编程和验证第二个子集可以继续，直到它被验证为软编程。 可以使用不同的步长来增加软编程信号的大小，具体取决于软编程和验证哪个子集。