公开(公告)号：US07112542B2

公开(公告)日：2006-09-26

申请号：US10330719

申请日：2002-12-27

申请人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

发明人： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/76

CPC分类号： H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

摘要： Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.

摘要翻译： 在导电元件之间形成绝缘材料的方法包括形成邻近导电电气部件的材料，该材料包括：部分蒸发物质以形成邻近导电电气部件的基体，所述基体在其内具有至少一个空隙。 其他方法包括在一对导电电气部件之间形成材料，包括：在一个质量块内形成一对导电的电气部件，并由该质量块的一大片分隔; 在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及使所述质量块的膨胀程度有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙。 一些实施例包括邻近导电电气部件的绝缘材料，这种材料包括基质和基质内的至少一个空隙。

公开(公告)号：USRE39194E1

公开(公告)日：2006-07-18

申请号：US10013333

申请日：2001-12-06

申请人： Guy Blalock

发明人： Guy Blalock

IPC分类号： B24B1/00 ,  B24B20/00

CPC分类号： B24B37/105 ,  B24B21/004 ,  B24B37/30 ,  B24B49/00

摘要： A method and apparatus for mechanical and/or chemical-mechanical planarization of microelectronic substrates. In one embodiment, an apparatus for controlling the planarizing characteristics of a microelectronic substrate has a carrier that may be positioned with respect to a polishing medium of a planarizing machine to move with respect to a microelectronic substrate during planarization. The apparatus may also have a modulator with a contact element, and the modulator may be attached to the carrier to position at least a portion of a contact element in front of a leading edge of the substrate by a selected distance during planarization. In operation, the modulator causes the contact element to selectively engage a region of the planarizing surface to modulate the contour of the planarizing surface during planarization.

摘要翻译： 用于微电子衬底的机械和/或化学机械平面化的方法和装置。 在一个实施例中，用于控制微电子衬底的平坦化特性的装置具有可以相对于平面化机器的抛光介质定位的载体，以在平坦化期间相对于微电子衬底移动。 该装置还可以具有带有接触元件的调制器，并且调制器可以附接到载体上，以在平坦化期间将接触元件的前缘的前边缘的至少一部分定位在选定距离之前。 在操作中，调制器使得接触元件选择性地接合平坦化表面的区域，以在平坦化期间调制平坦化表面的轮廓。

公开(公告)号：US20050285148A1

公开(公告)日：2005-12-29

申请号：US11217739

申请日：2005-09-01

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/48 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US20050227487A1

公开(公告)日：2005-10-13

申请号：US10822118

申请日：2004-04-08

申请人： Gurtej Sandhu ,  Guy Blalock

发明人： Gurtej Sandhu ,  Guy Blalock

IPC分类号： C23C14/58 ,  H01L21/20 ,  H01L21/285

CPC分类号： C23C14/5826 ,  H01L21/28512 ,  H01L21/28518

摘要： A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first material. The first and second materials are of different compositions, and are proximate one another at an interface. The first and second materials as being proximate one another at the interface are capable of reacting with one another at some minimum reaction temperature when in an inert non-plasma atmosphere at a pressure. The interface is provided at a processing temperature which is at least 50° C. below the minimum reaction temperature, and is provided at the pressure. With the interface at the processing temperature and at the pressure, the substrate is exposed to a plasma effective to impart a reaction of the first material with the second material to form a reaction product third material of the first and second materials over the first material. Other aspects and implementations are contemplated.

摘要翻译： 形成反应产物的方法包括提供包含第一材料的半导体衬底。 在第一材料上形成第二材料。 第一和第二材料具有不同的组成，并且在界面处彼此靠近。 在惰性非等离子体气氛中在压力下，在界面处彼此接近的第一和第二材料能够在某些最小反应温度下彼此反应。 界面的设置处于低于最低反应温度的至少50℃的处理温度，并且在压力下提供。 利用处理温度和压力下的界面，将基板暴露于等离子体中，以有效地使第一材料与第二材料发生反应，从而在第一材料上形成第一和第二材料的反应产物第三材料。 考虑了其他方面和实现。

公开(公告)号：US20050042824A1

公开(公告)日：2005-02-24

申请号：US10945774

申请日：2004-09-20

申请人： Shenlin Chen ,  Trung Doan ,  Guy Blalock ,  Lyle Breiner ,  Er-Xuan Ping

发明人： Shenlin Chen ,  Trung Doan ,  Guy Blalock ,  Lyle Breiner ,  Er-Xuan Ping

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L23/58

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/84 ,  Y10S438/964

摘要： The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

摘要翻译： 本发明包括形成坚固的含半导体的表面的方法。 在衬底上形成第一半导体层，并且在第一半导体层上形成第二半导体层。 随后，在第二半导体层上形成第三半导体层，并且在第三半导体层上形成含半导体的种子。 将种子退火以形成坚固的含半导体的表面。 第一，第二和第三半导体层是公共堆叠的一部分，并且可以在电容器结构的存储节点内一起使用。 本发明还包括包括粗糙表面的半导体结构。 坚固的表面可以是例如坚固的硅。

公开(公告)号：US06355566B1

公开(公告)日：2002-03-12

申请号：US09851684

申请日：2001-05-08

申请人： Bradley J. Howard ,  Mark E. Jost ,  Guy Blalock

发明人： Bradley J. Howard ,  Mark E. Jost ,  Guy Blalock

IPC分类号： H01L21461

CPC分类号： H01L21/7684 ,  H01L21/76819

摘要： A method for removing a surface defect from a dielectric layer during the formation of a semiconductor device comprises the steps of forming a dielectric layer having a hole therein, the dielectric also having a surface defect resulting from a previous manufacturing step such as chemical mechanical polish, contact with another surface during production, or from a manufacturing defect. A blanket conductive layer is then formed within the hole, within the surface defect, and over the dielectric layer. The conductive layer is etched from the surface of the dielectric using an etch which removes the conductive layer at a substantially faster rate than it removes the dielectric. This etch is stopped when the level of conductive material in the plug is flush with the upper surface of the dielectric. Next, the conductive and dielectric layers are etched using a dry or plasma etch which removes the conductive and dielectric layers at about the same rate. This etch continues until the surface defect in the dielectric layer is removed, thereby forming a nonrecessed plug.

摘要翻译： 在形成半导体器件期间从电介质层去除表面缺陷的方法包括以下步骤：在其中形成具有孔的电介质层，电介质还具有由以前的制造步骤（例如化学机械抛光）产生的表面缺陷， 在生产过程中或与制造缺陷相接触。 然后在孔内，表面缺陷内，以及介电层上方形成覆盖层的导电层。 使用蚀刻以比其去除电介质更快的速率去除导电层的蚀刻从电介质的表面蚀刻导电层。 当塞子中的导电材料的水平与电介质的上表面齐平时，停止该蚀刻。 接下来，使用干燥或等离子体蚀刻蚀刻导电和介电层，其以大约相同的速率去除导电和介电层。 该蚀刻继续，直到电介质层中的表面缺陷被去除，从而形成未加工的插塞。

公开(公告)号：US06222273B1

公开(公告)日：2001-04-24

申请号：US09016753

申请日：1998-01-30

申请人： Fernando Gonzalez ,  Guy Blalock

发明人： Fernando Gonzalez ,  Guy Blalock

IPC分类号： H01L2348

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of constructing a conductive via spacer within a dielectric layer located between a first metal layer and a second metal layer includes the steps of depositing a conductive spacer layer within the opening and over the first metal layer. A portion of the conductive spacer layer is removed to leave a conductive spacer within the opening. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers. The spacer preferably comprises a material selected from the group comprising refractory metal silicides and nitrides. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.

摘要翻译： 在位于第一金属层和第二金属层之间的电介质层内构造导电通孔间隔物的方法包括以下步骤：在开口内和第一金属层之上沉积导电隔离层。 去除导电间隔层的一部分以在开口内留下导电间隔物。 第二金属层沉积在间隔物上以完成第一和第二金属层之间的连接。 间隔物优选包含选自难熔金属硅化物和氮化物的材料。 间隔件优选是锥形的，并且通孔可以包括胶层，以改善间隔物对电介质层的粘附。

公开(公告)号：US6095159A

公开(公告)日：2000-08-01

申请号：US012155

申请日：1998-01-22

申请人： Guy Blalock ,  Kevin G. Donohoe

发明人： Guy Blalock ,  Kevin G. Donohoe

IPC分类号： H01J37/32 ,  H05H1/00

CPC分类号： H01J37/32174 ,  H01J37/321 ,  Y10S438/905

摘要： A method for controlling the voltage distribution of the standing wave impressed upon the coil of an inductively coupled plasma generator includes the steps of impressing a radio frequency voltage across the coil to establish a standing wave thereacross. A voltage profile is selected for the standing wave so as to control the location and amount of capacitive coupling. A circuit parameter is controlled to achieve the selected voltage profile. Proper selection of the voltage profile enhances process capabilities, decreases the time between cleans, minimizes component wear, and minimizes cleaning time. An apparatus for carrying out the disclosed method is also disclosed.

公开(公告)号：US6080675A

公开(公告)日：2000-06-27

申请号：US344435

申请日：1999-06-25

申请人： Kirk Prall ,  Guy Blalock

发明人： Kirk Prall ,  Guy Blalock

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/02043 ,  Y02P80/30 ,  Y10S438/906 ,  Y10S438/928

摘要： A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a covet layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer. Since the cover layer is deposited in a normal coating step of the process for fabricating a component on the wafer, it is deposited irrespective of whether the waste matter is removed from the wafer.

摘要翻译： 一种在晶片上制造半导体器件的方法，该半导体器件具有正面和背面的衬底，以及在衬底的背面积聚废物。 在本发明的方法中，在用于制造晶片上的部件的工艺的正常涂覆步骤中，在前侧上沉积蜂窝层。 覆盖层提供用于制造晶片正面上的部件的工艺中使用的材料，并在前侧形成阻挡层。 通过用合适的蚀刻剂从晶片的背面蚀刻废物，或者通过化学机械平坦化（“CMP”）工艺平坦化晶片的背面，从晶片的背面去除废物。 在去除步骤期间，覆盖层保护前侧，并且当废物从晶片的背面移除时，前侧上的任何装置特征不被损坏。 由于覆盖层在用于制造晶片上的部件的工艺的正常涂覆步骤中沉积，所以不管废物是否从晶片上移除，都被沉积。

公开(公告)号：US5980688A

公开(公告)日：1999-11-09

申请号：US107928

申请日：1998-06-30

申请人： Guy Blalock

发明人： Guy Blalock

IPC分类号： H01J37/32 ,  H05H1/00 ,  H05H1/46

CPC分类号： H01J37/32862 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/321 ,  H05H1/46 ,  Y10S438/905

摘要： A plasma reactor includes, a) an electrically insulative shell forming a reactor cavity, the reactor cavity having internal walls; b) inductive coils positioned externally of the cavity; and c) a capacitive coupling plate positioned externally of the cavity intermediate the cavity and inductive coils, a power source being operably connected with the capacitive coupling plate. A method of cleaning away material adhering to internal walls of a plasma reactor includes, a) injecting a cleaning gas into the reactor, the cleaning gas comprising a species which when ionized is reactive with material adhering to the internal plasma reactor walls; and b) generating a capacitive coupling effect between a pair of conductors, at least one of which is positioned externally of the plasma reactor, effective to both ionize the cleaning gas into the reactive ionized species and draw such ionized species in the direction of the external conductor to impact and clean away material adhering to the reactor internal walls. A combination dry etching and cleaning process is also disclosed.

摘要翻译： 等离子体反应器包括：a）形成反应器腔的电绝缘壳，所述反应器腔具有内壁; b）位于空腔外部的感应线圈; 以及c）电容耦合板，位于空腔外部的空腔和感应线圈之间，电源可操作地与电容耦合板连接。 清除附着在等离子体反应器内壁上的材料的方法包括：a）将清洁气体注入反应器中，该清洁气体包括当电离的材料与附着在内部等离子体反应器壁上的材料反应时的物质; 以及b）在一对导体之间产生电容耦合效应，其中至少一个导体位于等离子体反应器的外部，有效地将清洁气体电离成反应性离子化物质，并沿着外部方向抽取这些电离物质 导体冲击并清除附着在反应堆内壁上的材料。 还公开了一种组合式干蚀刻和清洁方法。