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公开(公告)号：US20170256221A1
公开(公告)日：2017-09-07
申请号：US14905024
申请日：2015-12-23
Inventor： Yafeng Li
CPC classification number: G09G3/3677 , G09G2300/0426 , G09G2300/0809 , G09G2310/0286 , G11C19/184 , G11C19/28
Abstract: A GOA substrate includes N shift register units. The first stage shift register unit outputs a scan signal pulse based on a first clock signal and a start signal. The last stage shift register unit outputs a scan signal pulse based on Mth clock signal and the start signal. The start signal has a pulse width starting from a falling edge of the Mth clock signal of the last stage shift register unit when scanning a first frame, and ending at a rising edge of the first clock signal of the first stage shift register unit when scanning a second frame. Since the first and last shift register units are used to drive a scan signal pulse based on the start signal, the present invention reduces the number of wires needed to transmit start signals and simplifies the complexity of the layout design.
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公开(公告)号：US12183300B2
公开(公告)日：2024-12-31
申请号：US17623328
申请日：2021-12-20
Inventor： Jian Tao , Shuai Feng , Yafeng Li , Zhong Peng , Jian He
IPC: G09G3/36
Abstract: A multiplexed display panel and device and a driving method for the multiplexed display panel are provided. At the moment when a switching switch is turned on, a potential of a fanout line corresponding to a data line connected to sub-pixels, into which an data signal is input, is adjusted to the same level as a potential of the data line as much as possible, and a potential difference between each fanout line and the corresponding data line is relatively small at the moment when the switching switch is turned on, so that an instantaneous current at this moment is greatly reduced without causing relatively large jump of the potential of the data line, a common electrode and back-plated indium tin oxide (ITO) greatly fluctuate, and then the surface noise generated by the display panel is turned on is greatly reduced.
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公开(公告)号：US12046173B2
公开(公告)日：2024-07-23
申请号：US17613064
申请日：2021-09-29
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/0297 , G09G2310/08
Abstract: The present application discloses a display panel and a display device. The display panel includes a plurality of multiplexing drive modules, a plurality of drive branches and M drive buses. By electrically connecting one drive bus to N drive branches, the number of used drive buses can be reduced, thereby reducing the number of output channels of a drive signal source. Sine the number of used drive buses is reduced, the multiplexing drive modules can complete transmission of a frame of data signals using a less number of times of time-divisional parts for switching on transistors.
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公开(公告)号：US10297203B2
公开(公告)日：2019-05-21
申请号：US15308557
申请日：2016-09-28
Inventor： Yafeng Li
IPC: G09G3/3266 , G09G3/36
Abstract: The present application discloses a scanning driving circuit and a flat display apparatus, the scanning driving circuit includes a plurality of cascaded scanning driving unit, each scanning driving unit including a forward and reverse scanning circuit for controlling the forward or reverse scanning; an input circuit to perform charging to the pull-up control signal point and the pull-down control signal point; a leakage prevention circuit to preform a process to the leakage of the input circuit; an output circuit to generate a scanning driving signal and output to the level scanning line to drive a pixel unit.
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公开(公告)号：US10249243B2
公开(公告)日：2019-04-02
申请号：US15506241
申请日：2016-12-30
Inventor： Yafeng Li
IPC: G09G3/3258 , G09G3/3266 , G09G3/36
Abstract: The present invention relates to a GOA circuit. The GOA circuit of the present invention comprises a plurality of GOA circuit units which are cascade coupled, wherein n is set to be a natural number larger than 0, and the nth level GOA circuit unit comprises: a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a fifth thin film transistor (T5), a sixth thin film transistor (T6), a seventh thin film transistor (T7), an eighth thin film transistor (T8), a ninth thin film transistor (T9), a tenth thin film transistor (T10), a first capacitor (C1) and a second capacitor (C2). Moreover, two control signals (Select1, Select2) are introduced. The present invention provides a new GOA circuit. The circuit possesses MLG function, which can effectively reduce the feedthrough and improve the Vcom uniformity in the panel to promote the quality of the image display.
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Patent Agency Ranking
公开(公告)号：US10146078B2
公开(公告)日：2018-12-04
申请号：US14889207
申请日：2015-08-12
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Yafeng Li
IPC: G02F1/1335 , G02F1/1368 , G02F1/1333 , G02F1/1339 , G02F1/1362 , G02F1/1343
Abstract: An array substrate for a liquid crystal display panel is disclosed. The array substrate includes a first substrate, a Lower Temperature Polycrystal Silicon (LTPS) Thin-Film-Transistor (TFT) disposed on the first substrate, a color photoresist layer disposed on the LTPS TFT, and multiple photo spacers disposed above the color photoresist layer. A liquid crystal display panel including the array substrate and a second substrate disposed oppositely to the array substrate is also disclosed. The present invention utilizes the second substrate to be aligned with the LTPS TFT array substrate in order to form the liquid crystal display panel. Because the second substrate is a bare substrate (without a pattern), when the second substrate is aligned with the array substrate, the alignment precision is not under consideration. Accordingly, apertures ratios of the liquid crystal display panel do not have difference.
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公开(公告)号：US10043477B2
公开(公告)日：2018-08-07
申请号：US15128106
申请日：2016-08-31
Inventor： Yafeng Li
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G2230/00 , G09G2300/0408 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
Abstract: The invention provides a GOA circuit, using the ninth and tenth TFTs and the resistor to control the voltage level of the third node, wherein ninth TFT having the gate connected to the m-th clock signal, the source connected to the first constant voltage, and the drain connected to one end of the resistor; the tenth TFT having the gate connected to the (m+2)-th clock signal, the source connected to the second constant voltage, and the drain connected to the other end of the resistor. Through the m-th and the (m+2)-th clock signal to control the ninth and the tenth TFTs to become conductive alternately, the present invention can charge and discharge the third node regularly to prevent the threshold voltage shift of the key TFT because the third node stays high for extended time, and ensure the stability of GOA circuit.
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公开(公告)号：US10043473B2
公开(公告)日：2018-08-07
申请号：US15128420
申请日：2016-08-30
Inventor： Yafeng Li
IPC: G09G3/36
CPC classification number: G09G3/3674 , G09G2310/0267 , G09G2310/0283 , G09G2310/0286 , G11C19/184 , G11C19/28
Abstract: The invention provides a GOA circuit, the forward-and-reverse scan control module of the GOA circuit comprising: a first TFT and a third TFT, the first TFT having the gate connected to the gate scan drive signal of the (n−1)-th GOA unit, the source connected to the first constant voltage, and the drain connected to a first node; and the third TFT having the gate connected to the gate scan drive signal of the (n+1)-th GOA unit, the source connected to the first constant voltage, and the drain connected to the first node. With the two TFTs to control the switching of forward and reverse scanning of the GOA circuit, the present invention eliminates two control signals without increasing the numbers of TFTs and capacitors. As such, the selection for IC is increased, which enables the realization of narrow border LCD.
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公开(公告)号：US09966029B2
公开(公告)日：2018-05-08
申请号：US14906708
申请日：2016-01-13
Inventor： Yafeng Li
IPC: G09G3/36 , G09G3/3266
CPC classification number: G09G3/3677 , G09G3/3266 , G09G3/3696 , G09G2300/0408 , G09G2300/0842 , G09G2300/0871 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
Abstract: A GOA circuit includes GOA circuit units. Each of the GOA circuit units at each stage includes an input control module, an output control module, and a pull-down module. The pull-down module includes a first transistor, a second transistor, a third transistor, and a resistor. The GOA circuit unit uses fewer transistors and fewer capacitors. Therefore, the GOA circuit unit proposed by the present invention is beneficial for being used in displays with a narrow bezel. In addition, the GOA circuit unit omits a capacitor so power generated after the capacitor is charged is reduced. It provides a beneficiary effect of reducing power of the whole GOA circuit.
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公开(公告)号：US09921673B2
公开(公告)日：2018-03-20
申请号：US14912601
申请日：2016-01-29
Inventor： Yafeng Li , Xiangyi Peng
IPC: G02F1/1333 , G06F3/041 , G02F1/1335 , G02F1/1368 , G02F1/1362 , G02F1/1343 , G02F1/1339
CPC classification number: G06F3/0412 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133514 , G02F1/13394 , G02F1/134309 , G02F1/134363 , G02F1/13439 , G02F1/136209 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , G02F2001/133357 , G02F2001/13396 , G02F2001/13398 , G02F2201/121 , G02F2201/123 , G02F2201/40 , G02F2202/104 , G06F3/044
Abstract: The present invention provides an in-cell touch display panel. In the in-cell touch display panel of the present invention, a first planarization layer (14) is solely arranged between a pixel electrode (15) and source/drain electrodes (45) located on one side of a TFT substrate (1) and the pixel electrode (15) is connected through a second via (141) formed in the first planarization layer (14) to the source/drain electrodes (45) so that compared to the prior art, the thickness of two passivation layers is omitted between the pixel electrode (15) and the source/drain electrodes (45) and negative influence caused by overlapping of vias between the first passivation layer (16) and the first planarization layer (14) and between the second passivation layer (18) and the first planarization layer (14) can be eliminated, whereby there is no need to take into consideration the relationship of the first planarization layer with respect to the first passivation layer and the second passivation layer in making a design so that the aperture ratio of the pixel can be greatly increased. Further, since the number of vias formed is reduced, the structure is simple and the manufacturing difficulty is lowered down to thereby improve product yield.
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