公开(公告)号：US07288808B2

公开(公告)日：2007-10-30

申请号：US10050334

申请日：2002-01-15

Applicant: Vishnu K. Agarwal ,  Garry A. Mercaldi

Inventor： Vishnu K. Agarwal ,  Garry A. Mercaldi

IPC: H01L27/108

CPC classification number: H01L28/55 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/84 ,  H01L28/90 ,  Y10S438/964

Abstract: A capacitor fabrication method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

Abstract translation: 电容器制造方法可以包括在衬底上形成第一电容器电极，第一电极具有每单位面积的内表面积和每单位面积的外表面积，其大于衬底的每单位面积的外表面积。 可以在电介质层上形成电容器电介质层和第二电容器电极。 该方法还可以包括在衬底上形成坚固的多晶硅，第一电极在坚固的多晶硅之上。 因此，第一电极的外表面积可以比不含第一电极包括多晶硅的衬底的外表面积大至少30％。

公开(公告)号：US07282666B2

公开(公告)日：2007-10-16

申请号：US10841857

申请日：2004-05-07

Applicant: Vishnu K. Agarwal ,  William A. Stanton

Inventor： Vishnu K. Agarwal ,  William A. Stanton

IPC: B23K26/067

CPC classification number: B23K26/0604 ,  B23K26/0622 ,  B23K26/38 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50

Abstract: A material processing system and method is disclosed for processing materials such as amorphous silicon in an annealing processes and lithography processes on a silicon wafer, as well as ablation processes. A first laser generates periodic pulses of radiation along a beam path directed at the target material. Similarly, at least one additional laser generates periodic pulses. A beam aligner redirects the beam path of the at least one laser, such that the beam from the at least one additional laser is directed at the target along a path colinear with the first laser's beam path. As a result, all the lasers are directed at the target along the same combined beam path. The periodic pulses of the at least one additional laser are delayed relative to the first laser such that multiple pulses impinge on the target within a single pulse cycle of any given laser.

Abstract translation: 公开了一种材料处理系统和方法，用于在硅晶片上的退火工艺和光刻工艺中处理诸如非晶硅的材料，以及消融工艺。 第一激光器沿着指向目标材料的光束路径产生周期性的辐射脉冲。 类似地，至少一个附加激光器产生周期性脉冲。 光束对准​​器重定向至少一个激光器的光束路径，使得来自至少一个附加激光器的光束沿着与第一激光束的光束路径共线的路径被引导到目标。 因此，所有的激光都沿相同的组合光束路径被引导到目标。 至少一个附加激光器的周期性脉冲相对于第一激光器被延迟，使得多个脉冲在任何给定激光器的单个脉冲周期内撞击目标物。

公开(公告)号：US07271092B2

公开(公告)日：2007-09-18

申请号：US11119370

申请日：2005-04-29

Applicant: Vishnu K. Agarwal ,  Gurtej S. Sandhu

Inventor： Vishnu K. Agarwal ,  Gurtej S. Sandhu

IPC: H01L21/44

CPC classification number: H01L21/28088 ,  H01L21/28061 ,  H01L21/76841 ,  H01L23/53257 ,  H01L29/4941 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

Abstract translation: 公开了一种包括TiN x B B y y的扩散阻挡层，用于保护集成晶体管中的栅极氧化物层。 可以通过首先形成TiN层然后将硼掺入到TiN层中来制造扩散阻挡层。 扩散阻挡层也可以通过使用包括硼的TDMAT工艺来形成TiN层的方法来制造。 扩散阻挡层也可以通过使用CVD工艺形成TiN x B层Y 3层来制造。 扩散阻挡层特别适用于通过CVD形成的钨或硅化钨导电层。

公开(公告)号：US07268072B2

公开(公告)日：2007-09-11

申请号：US11088311

申请日：2005-03-23

Applicant: Scott J. Deboer ,  Vishnu K. Agarwal

Inventor： Scott J. Deboer ,  Vishnu K. Agarwal

IPC: H01L21/4763

CPC classification number: H01L27/10855 ,  H01L21/76895 ,  H01L23/5283 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract translation: 使用中间金属插头来升高要与其接触的平台。 在所示的处理中，在叠层电容器附近形成部分位线插头，在电容器上形成层间电介质。 通过将形成在层间电介质上方的位线延伸到中间插塞的水平面，并且通孔填充金属来完成位线接触。 因此，要填充的通孔的高度被中间塞的高度减小。 在一个实施例中，中间塞略短于相邻的容器状电容器。 在另一个实施例中，中间插头与相邻的插头电容器一样高。

公开(公告)号：US07251387B2

公开(公告)日：2007-07-31

申请号：US10894268

申请日：2004-07-19

Applicant: Vishnu K. Agarwal

Inventor： Vishnu K. Agarwal

IPC: G02B6/12

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  G02B6/12007 ,  G02B6/30 ,  H01S3/06758

Abstract: The present technique relates to a method and apparatus for fabricating an optical integrated circuit amplifier with another type of optical integrated circuit. In optical networks, optical components exchange optical signals to communicate between different systems coupled to the optical components. The optical components may include optical integrated circuit amplifiers and other optical integrated circuits coupled together through optical paths. The optical integrated circuit amplifiers and other optical integrated circuits of the optical components are fabricated on the same substrate to reduce the cost of fabrication, maintenance and installation, while enhancing the performance of the optical component.

Abstract translation: 本技术涉及一种用于制造具有另一类型的光集成电路的光集成电路放大器的方法和装置。 在光网络中，光学部件交换光信号以在耦合到光学部件的不同系统之间进行通信。 光学部件可以包括通过光路耦合在一起的光学集成电路放大器和其它光学集成电路。 光学部件的光学集成电路放大器和其他光学集成电路被制造在相同的基板上，以降低制造，维护和安装的成本，同时提高光学部件的性能。

公开(公告)号：US07094657B1

公开(公告)日：2006-08-22

申请号：US09652841

申请日：2000-08-31

Applicant: Vishnu K. Agarwal

Inventor： Vishnu K. Agarwal

IPC: H01L21/20 ,  H01L21/8242

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/40 ,  Y10S438/957 ,  Y10S438/958

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract translation: 在包括第一导电层的半导体器件中，在其上沉积另外的层之前，用氮/氢等离子体处理第一导电层。 处理用氮气填充表面，从而防止氧被吸附到第一导电层的表面上。 在一个实施例中，第二导电层沉积到第一导电层上，并且如果不消除由于随后的热处理而在两层之间形成的氧化物，则等离子体处理减少。 在另一个实施例中，介电层沉积到第一导电层上，如果不消除第一导电层从电介质中掺入氧的能力，则等离子体处理减少。

公开(公告)号：US07084504B2

公开(公告)日：2006-08-01

申请号：US10687086

申请日：2003-10-16

Applicant: Vishnu K. Agarwal ,  Gurtej S. Sandhu

Inventor： Vishnu K. Agarwal ,  Gurtej S. Sandhu

IPC: H01L23/12

CPC classification number: H01L21/28088 ,  H01L21/28061 ,  H01L21/76841 ,  H01L23/53257 ,  H01L29/4941 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

Abstract translation: 公开了一种包括TiN x B B y y的扩散阻挡层，用于保护集成晶体管中的栅极氧化物层。 可以通过首先形成TiN层然后将硼掺入到TiN层中来制造扩散阻挡层。 扩散阻挡层也可以通过使用包括硼的TDMAT工艺来形成TiN层的方法来制造。 扩散阻挡层也可以通过使用CVD工艺形成TiN x B层Y 3层来制造。 扩散阻挡层特别适用于通过CVD形成的钨或硅化钨导电层。

公开(公告)号：US07049153B2

公开(公告)日：2006-05-23

申请号：US10421157

申请日：2003-04-23

Applicant: Vishnu K. Agarwal ,  Howard E. Rhodes

Inventor： Vishnu K. Agarwal ,  Howard E. Rhodes

IPC: H01L21/00

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

Abstract: Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.

Abstract translation: 使用铁电材料制成集成存储器电路，成千上万种电子和计算机产品的关键部件，其提供比其他材料更快的写入周期和更低的功率需求。 然而，本发明人已经认识到，例如，用于与聚合物一起工作的常规技术产生具有损害性能和制造产率的厚度变化的聚合物层。 因此，本发明人为基于聚合物的铁电存储器设计了独特的方法和结构。 一种示例性方法需要在衬底上形成绝缘层，形成两个或更多个第一导电结构，其中至少两个第一导电结构由间隙分开，在间隙内形成间隙填充结构，并形成基于聚合物的 间隙填充结构上的铁电层和第一导电结构。 在一些实施例中，间隙填充结构是聚合物，旋涂玻璃或流动填充氧化物。

公开(公告)号：US07006746B2

公开(公告)日：2006-02-28

申请号：US10233000

申请日：2002-08-29

Applicant: Guy T. Blalock ,  Howard E. Rhodes ,  Vishnu K. Agarwal ,  Gurtej Singh Sandhu ,  James S. Foresi ,  Jean-Francois Viens ,  Dale G. Fried

Inventor： Guy T. Blalock ,  Howard E. Rhodes ,  Vishnu K. Agarwal ,  Gurtej Singh Sandhu ,  James S. Foresi ,  Jean-Francois Viens ,  Dale G. Fried

IPC: G02B6/10

CPC classification number: G02F1/025 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12107 ,  G02B2006/12164 ,  G02F1/0147 ,  G02F2203/15

Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.

Abstract translation: 波导和谐振器形成在热光器件的下包层上，每个具有基本相等的形成高度。 此后，波导的形成高度被衰减。 以这种方式，波导和谐振器在波导和谐振器前面或彼此面对的区域（与现有技术相比）中的波导和谐振器之间的纵横比，从而恢复波导和光栅之间的同步性并允许更高的带宽配置 要使用的。 在形成谐振器和波导之后，通过光掩模和蚀刻波导来实现波导衰减。 在一个实施例中，在沉积上部包层之后进行光掩模和蚀刻。 另一方面，它是在沉积之前进行的。 还教导了具有这些波导的热光器件，热光封装和光纤系统。

公开(公告)号：US06953721B2

公开(公告)日：2005-10-11

申请号：US09797899

申请日：2001-03-01

Applicant: Vishnu K. Agarwal

Inventor： Vishnu K. Agarwal

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01G4/08 ,  H01G4/30

CPC classification number: H01L21/02183 ,  H01L21/022 ,  H01L21/02337 ,  H01L21/02356 ,  H01L27/1085 ,  H01L28/55

Abstract: The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received therebetween. The high K capacitor dielectric region has a high K substantially amorphous material layer and a high K substantially crystalline material layer. In one implementation, a capacitor forming method includes forming a first capacitor electrode layer over a substrate. A substantially amorphous first high K capacitor dielectric material layer is deposited over the first capacitor electrode layer. The substantially amorphous high K first capacitor dielectric material layer is converted to be substantially crystalline. After the converting, a substantially amorphous second high K capacitor dielectric material layer is deposited over the substantially crystalline first high K capacitor dielectric material layer. A second capacitor electrode layer is formed over the substantially amorphous second high K capacitor dielectric material layer.

Abstract translation: 本发明包括集成电路和形成电容器的方法。 在一个实施方式中，集成电路包括具有第一电容器电极，第二电容器电极和接收在其间的高K电容器电介质区域的电容器。 高K电容电介质区域具有高K基本无定形材料层和高K基本结晶材料层。 在一个实施方式中，电容器形成方法包括在衬底上形成第一电容器电极层。 在第一电容器电极层上沉积基本无定形的第一高K电容介电材料层。 基本无定形的高K第一电容器介电材料层被转换成基本上是结晶的。 在转换之后，在基本上晶体的第一高K电容介电材料层上沉积基本非晶的第二高K电容器介电材料层。 第二电容器电极层形成在基本无定形的第二高K电容电介质材料层上。