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    Copper alloy via structure
    32.
    发明授权
    Copper alloy via structure 有权
    铜合金通孔结构

    公开(公告)号：US6160315A

    公开(公告)日：2000-12-12

    申请号：US478721

    申请日：2000-01-06

    申请人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

    发明人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

    IPC分类号： C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

    CPC分类号： H01L21/76834 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/2855 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A copper via structure formed when copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide but also extends into the oxide a distance of about 100 nm. The alloying metal oxide having a thickness of about 6 nm on the oxide sidewalls encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.

    摘要翻译： 当铜和少量的合金金属如镁或铝形成的铜通孔结构在其表面的至少一部分上被分散在具有氧化物的基底上。 在沉积期间晶片保持在升高的温度下，或者溅射膜被退火而晶片不暴露于环境中。 由于高温，合金金属扩散到表面。 如果表面暴露于低的氧分压或接触二氧化硅，则镁或铝形成薄的稳定氧化物，但也延伸到氧化物中约100nm的距离。 在氧化物侧壁上具有约6nm厚度的合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障，以形成二氧化硅以上的粘合层，并且用作后续生长铜的种子层， 例如，通过电镀。

    Method of depositing a metal seed layer on semiconductor substrates
    34.
    发明申请
    Method of depositing a metal seed layer on semiconductor substrates 失效
    在半导体衬底上沉积金属种子层的方法

    公开(公告)号：US20050085068A1

    公开(公告)日：2005-04-21

    申请号：US10981319

    申请日：2004-11-03

    申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

    摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

    摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被腐蚀掉或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

    Barrier layer for electroplating processes
    35.
    发明授权
    Barrier layer for electroplating processes 有权
    电镀工艺的屏障层

    公开(公告)号：US06790776B2

    公开(公告)日：2004-09-14

    申请号：US10016255

    申请日：2001-12-10

    申请人： Peijun Ding ,  Tony Chiang ,  Tse-Yong Yao ,  Barry Chin

    发明人： Peijun Ding ,  Tony Chiang ,  Tse-Yong Yao ,  Barry Chin

    IPC分类号： C23C1434

    CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877

    摘要： The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.

    摘要翻译： 本发明通常提供了一种用于制备用于电化学沉积的表面的方法，其包括在表面上形成高导电阻挡层并在高导电阻挡层上沉积种子层。 本发明的另一方面提供一种用于在衬底上填充结构的方法，包括在所述结构的一个或多个表面上沉积高电导阻挡层，在所述阻挡层上沉积晶种层，以及电化学沉积金属以填充所述结构 。

    Method of depositing a metal seed layer on semiconductor substrates
    36.
    发明申请
    Method of depositing a metal seed layer on semiconductor substrates 有权
    在半导体衬底上沉积金属种子层的方法

    公开(公告)号：US20070020922A1

    公开(公告)日：2007-01-25

    申请号：US11450703

    申请日：2006-06-09

    申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

    摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

    摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻的材料层的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。 使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

    Two step method for filling holes with copper
    38.
    发明申请
    Two step method for filling holes with copper 审中-公开
    用铜填充孔的两步法

    公开(公告)号：US20050032369A1

    公开(公告)日：2005-02-10

    申请号：US10940518

    申请日：2004-09-14

    申请人： Peijun Ding ,  Tony Chiang ,  Barry Chin

    发明人： Peijun Ding ,  Tony Chiang ,  Barry Chin

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/28

    CPC分类号： H01L21/76877 ,  H01L21/2855

    摘要： A method of filling trenches or vias on a semiconductor workpiece surface with copper using sputtering techniques. A copper wetting layer and a copper fill layer may both be applied by sputtering techniques. The thin wetting layer of copper is applied at a substrate surface temperature ranging between about 20° C. to about 250° C., and subsequently the temperature of the substrate is increased, with the application of the sputtered copper fill layer beginning at above at least about 200° C. and continuing while the substrate temperature is increased to a temperature as high as about 600° C. Preferably the substrate temperature during application of the sputtered fill layer ranges between about 300° C. and about 500° C.

    摘要翻译： 使用溅射技术用铜填充半导体工件表面上的沟槽或通孔的方法。 铜浸润层和铜填充层都可以通过溅射技术施加。 在约20℃至约250℃范围内的衬底表面温度下施加铜的薄润湿层，随后随着溅射铜填充层的应用从上方开始施加，衬底的温度升高 至少约200℃，并且在衬底温度升高至高达约600℃的温度下继续进行。优选地，溅射填充层施加期间的衬底温度范围为约300℃至约500℃。

    Ultra-low resistivity tantalum films and methods for their deposition
    39.
    发明授权
    Ultra-low resistivity tantalum films and methods for their deposition 失效
    超低电阻率钽薄膜及其沉积方法

    公开(公告)号：US06458255B2

    公开(公告)日：2002-10-01

    申请号：US09770934

    申请日：2001-01-25

    申请人： Tony Chiang ,  Peijun Ding ,  Barry Chin

    发明人： Tony Chiang ,  Peijun Ding ,  Barry Chin

    IPC分类号： C23C1434

    CPC分类号： H01L21/76843 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/28556 ,  H01L21/318 ,  H01L21/76864 ,  Y10T428/31678

    摘要： We have discovered that, by depositing a tantalum layer upon a substrate at a temperature of at least 325° C., it is possible to obtain an ultra low resistivity which is lower than that previously published in the literature. In addition, it is possible deposit a TaxNy film having an ultra low resistivity by depositing the TaxNy film upon a substrate at a temperature of at least 275° C., wherein x is 1 and y ranges from about 0.05 to about 0.18. These films having an ultra low resistivity are obtained at temperatures far below the previously published temperatures for obtaining higher resistivity films. A combination of elevated substrate temperature and ion bombardment of the film surface during deposition enables the use of lower substrate temperatures while maintaining optimum film properties. In another development, we have discovered that the ultra low resistivity tantalum and TaxNy films produced by the method of the present invention also exhibit particularly low residual stress, so that they are more stable and less likely to delaminate from adjacent layers in a multilayered semiconductor structure. Further, these films can be chemical mechanical polished at significantly higher rates (at least 40% higher rates) than the higher resistivity tantalum and TaxNy films previously known in the industry. This is particularly useful in damascene processes when copper is used as the interconnect metal, since it reduces the possibility of copper dishing during a polishing step.

    摘要翻译： 我们已经发现，通过在至少325℃的温度下在基底上沉积钽层，可以获得低于文献以前公开的超低电阻率。 此外，可以通过在至少275℃的温度下将TaxNy膜沉积在基底上来沉积具有超低电阻率的TaxNy膜，其中x为1，y为约0.05至约0.18。 在远低于先前发表的温度的温度下获得具有超低电阻率的这些膜，以获得更高电阻率的膜。 在沉积期间升高的基板温度和膜表面的离子轰击的组合使得能够使用较低的基板温度同时保持最佳的膜性质。 在另一个发展中，我们已经发现，通过本发明的方法生产的超低电阻率的钽和TaxNy膜也表现出特别低的残余应力，使得它们在多层半导体结构中比较相邻层更稳定和更不可能分层 。 此外，这些膜可以比以前在工业上已知的较高电阻率的钽和TaxNy膜以更高的速率（至少高40％的速率）进行化学机械抛光。 当使用铜作为互连金属时，这对于镶嵌工艺特别有用，因为它减少了在抛光步骤期间铜凹陷的可能性。

    Copper alloy seed layer for copper metallization
    40.
    发明授权
    Copper alloy seed layer for copper metallization 失效
    铜合金种子层用于铜金属化

    公开(公告)号：US06387805B2

    公开(公告)日：2002-05-14

    申请号：US08878143

    申请日：1997-06-18

    申请人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    发明人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    IPC分类号： H01L2144

    CPC分类号： H01L21/76843 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A copper metallization structure and its method of formation in which a layer of a copper alloy, such as Cu—Mg or Cu—Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

    摘要翻译： 在铜合金层上沉积铜基金属化结构及其形成方法，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。 优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到 电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。