公开(公告)号：US20220223478A1

公开(公告)日：2022-07-14

申请号：US17712486

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chung-Liang CHENG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.

公开(公告)号：US20220102218A1

公开(公告)日：2022-03-31

申请号：US17197936

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L21/8234 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.

公开(公告)号：US20210398900A1

公开(公告)日：2021-12-23

申请号：US17193807

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/48

Abstract: A semiconductor process system etches thin films on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted remaining thin-film data that matches the target thin-film data. The process system then uses the static and dynamic process conditions data for the next etching process.

公开(公告)号：US20210341390A1

公开(公告)日：2021-11-04

申请号：US17169101

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: G01N21/64 ,  G01N21/95 ,  G06F30/27 ,  G06N3/08 ,  C23C14/54

Abstract: A thin-film deposition system deposits a thin-film on a wafer. A radiation source irradiates the wafer with excitation light. An emissions sensor detects an emission spectrum from the wafer responsive to the excitation light. A machine learning based analysis model analyzes the spectrum and detects contamination of the thin-film based on the spectrum.

公开(公告)号：US20210098457A1

公开(公告)日：2021-04-01

申请号：US16585267

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  I-Ming CHANG ,  Ziwei FANG ,  Huang-Lin CHAO

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.

公开(公告)号：US20210057550A1

公开(公告)日：2021-02-25

申请号：US16548446

申请日：2019-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  I-Ming CHANG ,  Hsiang-Pi CHANG ,  Hsueh-Wen TSAU ,  Ziwei FANG ,  Huang-Lin CHAO

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor layer on a semiconductor substrate, forming an interfacial layer on the semiconductor layer, forming a first gate dielectric layer on the interfacial layer, introducing fluorine on the first gate dielectric layer, annealing the first gate dielectric layer, forming a second gate dielectric layer on the first gate dielectric layer, introducing fluorine on the second gate dielectric layer, annealing the second gate dielectric layer, and forming a gate stack structure on the second gate dielectric layer.

公开(公告)号：US20200328213A1

公开(公告)日：2020-10-15

申请号：US16911672

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/49 ,  H01L21/02

Abstract: A semiconductor device is provided. The semiconductor device includes first nanostructures vertically stacked over a first region of a substrate, a gate dielectric layer wrapping around the first nanostructures, a first oxygen blocking layer wrapping around the gate dielectric layer in the first region, a first-type work function layer wrapping around the first oxygen blocking layer in the first region, a second oxygen blocking layer wrapping around the first-type work function layer in the first region, and a second-type work function layer wrapping around the second oxygen blocking layer in the first region.

公开(公告)号：US20200273985A1

公开(公告)日：2020-08-27

申请号：US16285595

申请日：2019-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer over an inner wall and a bottom of the trench. The method includes forming a mask layer over the gate dielectric layer over the bottom. The method includes removing the gate dielectric layer over the inner wall. The method includes removing the mask layer. The method includes forming a gate electrode in the trench.

公开(公告)号：US20200152746A1

公开(公告)日：2020-05-14

申请号：US16277262

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Wen TSAU ,  Chun-I WU ,  Ziwei FANG ,  Huang-Lin CHAO ,  I-Ming CHANG ,  Chung-Liang CHENG ,  Chih-Cheng LIN

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/532

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

公开(公告)号：US20200043739A1

公开(公告)日：2020-02-06

申请号：US16596617

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Ying LIN ,  Cheng-Yi WU ,  Alan TU ,  Chung-Liang CHENG ,  Li-Hsuan CHU ,  Ethan HSIAO ,  Hui-Lin SUNG ,  Sz-Yuan HUNG ,  Sheng-Yung LO ,  C.W. CHIU ,  Chih-Wei Hsieh ,  Chin-Szu LEE

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/417 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.