公开(公告)号：US20220123207A1

公开(公告)日：2022-04-21

申请号：US17074843

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Chang-Chih Huang ,  Yuan-Tai Tseng ,  Kuo-Chyuan Tzeng ,  Yihuei Zhu

IPC: H01L45/00 ,  H01L27/24

Abstract: Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.

公开(公告)号：US11158797B2

公开(公告)日：2021-10-26

申请号：US16009327

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L27/24

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

公开(公告)号：US11005037B2

公开(公告)日：2021-05-11

申请号：US15647579

申请日：2017-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L49/02

Abstract: A method of manufacturing an integrated circuit device. In the method, a plurality of contacts are formed over a substrate, and one or more bottom electrode layers are formed over the plurality of contacts. A first dielectric layer is formed such that a first base region of the first dielectric layer is in contact with the one or more bottom electrode layers and a second base region of the first dielectric layer is not in contact with the one or more bottom electrode layers. One or more top electrode layers are formed over the first dielectric layer. Patterning is then performed by etching through the one or more top electrode layers and by etching through the first dielectric layer to form a metal-insulator-metal structure. The patterning removes a portion of the second base region, but does not remove the first base region.

公开(公告)号：US20200075855A1

公开(公告)日：2020-03-05

申请号：US16674445

申请日：2019-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.

公开(公告)号：US10164181B2

公开(公告)日：2018-12-25

申请号：US15489863

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Hsueh Yang ,  Yuan-Tai Tseng ,  Yi-Jen Tsai ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L43/08

Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode.

公开(公告)号：US09768220B2

公开(公告)日：2017-09-19

申请号：US14253025

申请日：2014-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Yu-Hsing Chang ,  Ming Chyi Liu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/14638 ,  H01L21/76232 ,  H01L27/14607 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L27/14692 ,  H01L29/0649

Abstract: Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench.

公开(公告)号：US09741868B2

公开(公告)日：2017-08-22

申请号：US14688011

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/78 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7831

Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has a memory gate with a flat top surface. A memory gate spacer is arranged directly above the memory gate having a lateral dimension smaller than that of the memory gate. The memory gate spacer has an inner sidewall disposed along an upper portion of a charge trapping layer and an outer sidewall recessed back laterally relative to an outer sidewall of the memory gate. In some embodiments, a dielectric liner is continuously lined the outer sidewall of the memory gate, extending on a portion of the top surface of the memory gate not covered by the memory gate spacer, and extending upwardly along the outer sidewall of the memory gate spacer.

公开(公告)号：US09589976B2

公开(公告)日：2017-03-07

申请号：US14688201

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/12 ,  H01L27/01 ,  H01L27/115 ,  H01L21/28 ,  H01L23/48 ,  H01L29/88 ,  H01L21/306

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/30625 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344

Abstract: The present disclosure relates to an integrated circuit (IC), including, a flash memory device region, including a pair of split-gate flash memory cells arranged over a semiconductor substrate. The pair of split gate flash memory cells respectively have a control gate (CG) including a polysilicon gate and an overlying silicide layer. A periphery circuit including, one or more high-k metal gate (HKMG) transistors are arranged over the semiconductor substrate at a position laterally offset from the flash memory device region. The one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer. A method of manufacturing the IC is also provided.

Abstract translation: 本公开涉及一种集成电路（IC），其包括闪存器件区域，其包括布置在半导体衬底上的一对分裂栅极闪存单元。 一对分裂栅极闪存单元分别具有包括多晶硅栅极和上覆硅化物层的控制栅极（CG）。 包括一个或多个高k金属栅极（HKMG）晶体管的外围电路在横向偏离闪存器件区域的位置上布置在半导体衬底的上方。 一个或多个HKMG晶体管具有金属栅电极，其上表面低于硅化物层的上表面。 还提供了一种制造IC的方法。

公开(公告)号：US09570454B2

公开(公告)日：2017-02-14

申请号：US14749970

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yu-Hsing Chang ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/7851

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract translation: 本公开涉及具有FinFET器件和嵌入式闪存器件的集成芯片及其形成方法。 在一些实施例中，集成芯片具有与逻辑区域横向分离的逻辑区域和存储区域。 逻辑区域具有从半导体衬底向外突出的半导体材料的第一多个翅片。 栅电极设置在半导体材料的第一多个散热片上。 存储区域具有从半导体衬底向外延伸的第二多个半导体材料翅片。 嵌入式闪存单元被布置在半导体材料的第二多个鳍上。 所得到的集成芯片结构提供了良好的性能，因为它包含FinFET器件和嵌入式闪存器件。

公开(公告)号：US20170018562A1

公开(公告)日：2017-01-19

申请号：US15277137

申请日：2016-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a flash memory cell. In some embodiments, the flash memory cell has a control gate arranged over a substrate, and a select gate separated from the substrate by a gate dielectric layer. A charge trapping layer has a first portion disposed between the select gate and the control gate, and a second portion arranged under the control gate. A first control gate spacer is arranged on the second portion of the charge trapping layer. A second control gate spacer is arranged on the second portion of the charge trapping layer and is separated from the control gate by the first control gate spacer.

Abstract translation: 本公开涉及闪存单元。 在一些实施例中，快闪存储器单元具有布置在衬底上的控制栅极，以及通过栅极电介质层与衬底分离的选择栅极。 电荷捕获层具有设置在选择栅极和控制栅极之间的第一部分和布置在控制栅极下方的第二部分。 第一控制栅极间隔物布置在电荷俘获层的第二部分上。 第二控制栅极间隔物布置在电荷俘获层的第二部分上，并且通过第一控制栅极隔离物与控制栅极分离。