公开(公告)号：US20200098969A1

公开(公告)日：2020-03-26

申请号：US16413839

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Chun-Ren Cheng ,  Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yan-Jie Liao

IPC: H01L41/08 ,  H01L41/047 ,  H01L41/297

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

公开(公告)号：US20170343498A1

公开(公告)日：2017-11-30

申请号：US15216853

申请日：2016-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Yi-Hsien Chang ,  Chun-Ren Cheng ,  Jui-Cheng Huang ,  Shih-Fen Huang ,  Tung-Tsun Chen ,  Ching-Hui Lin

IPC: G01N27/04 ,  H01L21/768 ,  H01L23/522 ,  H01L29/786

Abstract: A biosensor with a heater embedded therein is provided. A semiconductor substrate comprises a source region and a drain region. The heater is under the semiconductor substrate. A sensing well is over the semiconductor substrate, laterally between the source region and the drain region. A sensing layer lines the sensing well. A method for manufacturing the biosensor is also provided.

公开(公告)号：US11730058B2

公开(公告)日：2023-08-15

申请号：US16413839

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Chun-Ren Cheng ,  Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yan-Jie Liao

IPC: H01L41/193 ,  H01L41/08 ,  H01L41/113 ,  D01F6/62 ,  H10N30/00 ,  H10N30/04 ,  H10N30/067 ,  H10N30/87 ,  H10N30/063

CPC classification number: H10N30/10513 ,  H10N30/04 ,  H10N30/067 ,  H10N30/877 ,  H10N30/063

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

公开(公告)号：US11588095B2

公开(公告)日：2023-02-21

申请号：US16421810

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Fu-Chun Huang

IPC: H01L41/113 ,  G01N27/414 ,  H01L41/33 ,  H01L41/053 ,  H01L41/27 ,  H01L41/047

Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.

公开(公告)号：US11320395B2

公开(公告)日：2022-05-03

申请号：US16900989

申请日：2020-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Jui-Cheng Huang ,  Shih-Fen Huang ,  Tung-Tsun Chen ,  Yu-Jie Huang ,  Fu-Chun Huang

IPC: G01N27/414 ,  H01L23/31 ,  H01L23/522 ,  H01L23/64 ,  H01L29/786 ,  H01L21/8234 ,  H01L23/29

Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.

公开(公告)号：US11289568B2

公开(公告)日：2022-03-29

申请号：US16410259

申请日：2019-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Wen-Chuan Tai ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yen-Wen Chen ,  Anderson Lin ,  Fu-Chun Huang ,  Chun-Ren Cheng ,  Ivan Hua-Shu Wu ,  Fan Hu ,  Ching-Hui Lin ,  Yan-Jie Liao

IPC: H01L49/02 ,  H01L23/58 ,  H01L23/00

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.

公开(公告)号：US20210389273A1

公开(公告)日：2021-12-16

申请号：US16900989

申请日：2020-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Jui-Cheng Huang ,  Shih-Fen Huang ,  Tung-Tsun Chen ,  Yu-Jie Huang ,  Fu-Chun Huang

IPC: G01N27/414 ,  H01L23/31 ,  H01L23/522 ,  H01L23/29 ,  H01L23/64 ,  H01L29/786 ,  H01L21/8234

Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.

公开(公告)号：US11107899B2

公开(公告)日：2021-08-31

申请号：US16837401

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US10984211B1

公开(公告)日：2021-04-20

申请号：US16656882

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Fu-Chun Huang

IPC: G06K9/00 ,  H01L41/113 ,  G01N27/414

Abstract: The structure of a semiconductor device with an array of bioFET sensors, a biometric fingerprint sensor, and a temperature sensor and a method of fabricating the semiconductor device are disclosed. A method for fabricating the semiconductor device includes forming a gate electrode on a first side of a semiconductor substrate, forming a channel region between source and drain regions within the semiconductor substrate, and forming a piezoelectric sensor region on a second side of the semiconductor substrate. The second side is substantially parallel and opposite to the first side. The method further includes forming a temperature sensing electrode on the second side during the forming of the piezoelectric sensor region, forming a sensing well on the channel region, and binding capture reagents on the sensing well.

公开(公告)号：US09601411B2

公开(公告)日：2017-03-21

申请号：US14963235

申请日：2015-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Alexander Kalnitsky ,  Hsiao-Chin Tuan ,  Shih-Fen Huang ,  Hsin-Li Cheng ,  Felix Ying-Kit Tsui

IPC: H01L29/74 ,  H01L31/111 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.