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    Fully self-aligned interconnect structure
    31.
    发明授权
    Fully self-aligned interconnect structure 有权

    公开(公告)号：US11361994B2

    公开(公告)日：2022-06-14

    申请号：US16895338

    申请日：2020-06-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Ping Chen ,  Shau-Lin Shue ,  Min Cao

    IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/522

    Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

    Interconnect strucutre with protective etch-stop
    32.
    发明授权
    Interconnect strucutre with protective etch-stop 有权

    公开(公告)号：US11355390B2

    公开(公告)日：2022-06-07

    申请号：US16876465

    申请日：2020-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shao-Kuan Lee ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Cheng-Chin Lee

    IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.

    Selective deposition of barrier layer
    33.
    发明授权
    Selective deposition of barrier layer 有权

    公开(公告)号：US11251073B2

    公开(公告)日：2022-02-15

    申请号：US16837968

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L21/786 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306

    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

    Method with CMP for metal ion prevention
    34.
    发明授权
    Method with CMP for metal ion prevention 有权

    公开(公告)号：US11211256B2

    公开(公告)日：2021-12-28

    申请号：US16801526

    申请日：2020-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/67 ,  C09G1/02 ,  H01L21/3213

    Abstract: The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.

    Methods of performing chemical-mechanical polishing process in semiconductor devices
    35.
    发明授权
    Methods of performing chemical-mechanical polishing process in semiconductor devices 有权

    公开(公告)号：US11152255B2

    公开(公告)日：2021-10-19

    申请号：US16712430

    申请日：2019-12-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L21/321 ,  H01L23/535 ,  H01L23/532

    Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

    Semiconductor device and manufacturing method thereof
    37.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11127680B2

    公开(公告)日：2021-09-21

    申请号：US15632184

    申请日：2017-06-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shih-Kang Fu ,  Hsien-Chang Wu ,  Li-Lin Su ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528

    Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

    CAPPING LAYER OVERLYING DIELECTRIC STRUCTURE TO INCREASE RELIABILITY
    38.
    发明申请
    CAPPING LAYER OVERLYING DIELECTRIC STRUCTURE TO INCREASE RELIABILITY 有权

    公开(公告)号：US20210193566A1

    公开(公告)日：2021-06-24

    申请号：US16885378

    申请日：2020-05-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

    IPC: H01L23/522 ,  H01L23/538 ,  H01L21/768

    Abstract: Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.

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