公开(公告)号：US20220351939A1

公开(公告)日：2022-11-03

申请号：US17245724

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01J37/305 ,  H01J37/08

Abstract: The present disclosure relates to an ion beam etching (IBE) system including a plasma chamber configured to provide plasma, a screen grid, an extraction grid, an accelerator grid, and a decelerator grid. The screen grid receives a screen grid voltage to extract ions from the plasma within the plasma chamber to form an ion beam through a hole. The extraction grid receives an extraction grid voltage, where a voltage difference between the screen grid voltage and the extraction grid voltage determines an ion current density of the ion beam. The accelerator grid receives an accelerator grid voltage. A voltage difference between the extraction grid voltage and the accelerator grid voltage determines an ion beam energy for the ion beam. The IBE system can further includes a deflector system having a first deflector plate and a second deflector plate around a hole to control the direction of the ion beam.

公开(公告)号：US11437371B2

公开(公告)日：2022-09-06

申请号：US16925718

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/822

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

公开(公告)号：US11282711B2

公开(公告)日：2022-03-22

申请号：US16944653

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  H01L21/02 ,  H01J37/32

Abstract: The present disclosure describes methods and systems for plasma-assisted etching of a metal oxide. The method includes modifying a surface of the metal oxide with a first gas, removing a top portion of the metal oxide by a ligand exchange reaction, and cleaning the surface of the metal oxide with a second gas.

公开(公告)号：US11201229B2

公开(公告)日：2021-12-14

申请号：US16657224

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Li-Te Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the dummy gate stack. The spacer element has an inner spacer and a dummy spacer, and the inner spacer is between the dummy spacer and the dummy gate stack. The method also includes forming a dielectric layer to surround the spacer element and the dummy gate stack and replacing the dummy gate stack with a metal gate stack. The method further includes removing the dummy spacer of the spacer element to form a recess between the inner spacer and the dielectric layer. In addition, the method includes forming a sealing element to seal the recess such that a sealed hole is formed between the metal gate stack and the dielectric layer.

公开(公告)号：US11152491B2

公开(公告)日：2021-10-19

申请号：US16299531

申请日：2019-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.

公开(公告)号：US11107904B2

公开(公告)日：2021-08-31

申请号：US16592281

申请日：2019-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

Abstract: A method of fabricating a semiconductor device includes forming a structure including multiple nanowires vertically stacked above a substrate; depositing a dielectric material layer wrapping around the nanowires; performing a treatment process to a surface portion of the dielectric material layer; selectively etching the surface portion of the dielectric material layer; repeating the steps of performing the treatment process and selectively etching until the nanowires are partially exposed; and forming a gate structure engaging the nanowires.