公开(公告)号：US10269915B2

公开(公告)日：2019-04-23

申请号：US15615901

申请日：2017-06-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tai-I Yang ,  Yung-Chih Wang ,  Shin-Yi Yang ,  Chih-Wei Lu ,  Hsin-Ping Chen ,  Shau-Lin Shue

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/43 ,  H01L29/12 ,  H01L29/06 ,  H01L21/768

摘要： A vertical MOS transistor includes a substrate, a metal line disposed on the substrate, a semiconductor pillar disposed on and in contact with the metal line, a gate dielectric layer disposed surrounding the semiconductor pillar, a metal gate disposed surrounding a portion of the semiconductor pillar, and a gate electrode disposed in contact with the metal gate. In some embodiments, a width of an end of the gate electrode in contact with the metal gate is narrower than a width of an end of the gate electrode away from the metal gate.

公开(公告)号：US20180138076A1

公开(公告)日：2018-05-17

申请号：US15353850

申请日：2016-11-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5283

摘要： A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.

公开(公告)号：US20170194258A1

公开(公告)日：2017-07-06

申请号：US15463617

申请日：2017-03-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC分类号： H01L23/528 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a method for forming an interconnect structure. In some embodiments, the method may be performed by forming an opening within a sacrificial layer. The sacrificial layer is over a substrate. A conductive material is formed within the opening and over the sacrificial layer. The conductive material within the opening defines a conductive body. The conductive material is patterned to define a conductive projection extending outward from the conductive body. The sacrificial layer is removed and a dielectric material is formed surrounding the conductive body and the conductive projection.

公开(公告)号：US11171284B2

公开(公告)日：2021-11-09

申请号：US16914296

申请日：2020-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei-Hao Liao ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

摘要： A memory device includes a bottom electrode, an MTJ stack, and a top electrode. The bottom electrode has a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall. The MTJ stack is over the bottom electrode. The MTJ stack includes a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer. The bottom magnetic layer has a sidewall coterminous with the upper sidewall of the bottom electrode. The top magnetic layer has a sidewall laterally set back from the upper sidewall of the bottom electrode. The top electrode is over the MTJ stack.

公开(公告)号：US10804143B2

公开(公告)日：2020-10-13

申请号：US16458399

申请日：2019-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC分类号： H01L21/768 ,  H01L23/528

摘要： A semiconductor structure includes an integrated circuit, a first dielectric layer, an etching stop layer, a barrier layer, a conductive layer, and a second dielectric layer. The first dielectric layer is over the integrated circuit. The etching stop layer is over the first dielectric layer. The barrier layer has an upper portion extending along a top surface of the etching stop layer and a lower portion extending downwardly from the upper portion along a sidewall of the etching stop layer and a sidewall of the first dielectric layer. The conductive layer is over the barrier layer and having a void region extending through the conductive layer, the barrier layer and the etching stop layer. The second dielectric layer is over the conductive layer and the void region.

公开(公告)号：US10340181B2

公开(公告)日：2019-07-02

申请号：US15353850

申请日：2016-11-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC分类号： H01L21/768 ,  H01L23/528

摘要： A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.

公开(公告)号：US20160254225A1

公开(公告)日：2016-09-01

申请号：US15153967

申请日：2016-05-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC分类号： H01L23/538 ,  H01L29/06 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body. The integrated circuit also has a projection disposed over the conductive body. The projection has tapered sidewalls that cause a lower surface of the projection to have a greater width than an upper surface of the projection and a smaller width than an upper surface of the conductive body. A dielectric material surrounds the conductive body and the projection.

摘要翻译： 本公开涉及集成电路。 集成电路具有设置在衬底上的导电体。 导电体具有锥形侧壁，其导致导电体的上表面具有比导电体的下表面更大的宽度。 集成电路还具有设置在导电体上的突起。 突起具有锥形侧壁，其使得突出部的下表面具有比突起的上表面更大的宽度，并且具有比导电体的上表面更小的宽度。 电介质材料围绕导电体和突起。