公开(公告)号：US20240345944A1

公开(公告)日：2024-10-17

申请号：US18634559

申请日：2024-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KI-HEUNG KIM ,  Taeyoung Oh ,  Taekwoon Kim ,  Jinseong Yun ,  Yoonjae Jeong ,  Hyongryol Hwang

IPC: G06F12/02

CPC classification number: G06F12/0223 ,  G06F2212/202

Abstract: A method of operating a memory configured to communicate with a memory controller, the method includes: temporarily storing a unique identification (ID) for each of a plurality of memory devices included in the memory to each of the plurality of memory devices; selecting a target memory device from among the plurality of memory devices; and permanently or substantially permanently programming, in the target memory device, a unique ID corresponding to the target memory device.

公开(公告)号：US12073910B2

公开(公告)日：2024-08-27

申请号：US18169769

申请日：2023-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongcheol Kim ,  Hyunsung Shin ,  Hohyun Shin ,  Taeyoung Oh ,  Kyungsoo Ha

IPC: G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C11/408

CPC classification number: G11C7/1012 ,  G06F3/0619 ,  G11C11/4093 ,  G11C11/4096 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/4082 ,  G11C2207/005

Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

公开(公告)号：US20230420033A1

公开(公告)日：2023-12-28

申请号：US18196703

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongcheol Kim ,  Kiheung Kim ,  Taeyoung Oh ,  Kyungho Lee ,  Hyongryol Hwang

IPC: G11C11/4078 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: G11C11/4078 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/4094

Abstract: A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.

公开(公告)号：US20230326504A1

公开(公告)日：2023-10-12

申请号：US18160597

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoung Oh

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/109

Abstract: A semiconductor device includes an input/output interface with a first data input/output pin, a plurality of second data input/output pins, and a write clock signal pin, which is configured to receive a write clock signal from a memory controller. The first data input/output pin is configured to receive write training data from the memory controller during a write training operation, and the plurality of second data input/output pins feed result values of the write training to the memory controller. This write training is performed by the semiconductor device using the write clock signal and the write training data.

公开(公告)号：US20230305706A1

公开(公告)日：2023-09-28

申请号：US18169151

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoung Oh

IPC: G06F3/06 ,  G11C11/4076

CPC classification number: G06F3/061 ,  G11C11/4076 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method of operating a memory device includes receiving, from a memory controller, an operation command that is synchronized with a clock signal, receiving a data clock signal having a full-rate frequency and a synchronization pattern provided by at least one of a plurality of data signals. The clock signal and the data clock signal are then synchronized using a synchronization operation based on the synchronization pattern. The data clock signal may be received after a first delay time passes from a time point at which the operation command is received. The first delay time is a delay time necessary to prepare the synchronization operation.

公开(公告)号：US20190180795A1

公开(公告)日：2019-06-13

申请号：US16275396

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Taeyoung Oh

IPC: G11C5/14 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3287

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.

公开(公告)号：US10090039B2

公开(公告)日：2018-10-02

申请号：US15678436

申请日：2017-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyeon Doo ,  Taeyoung Oh ,  Namjong Kim ,  Chulsung Park

IPC: G11C11/406 ,  G11C7/04

Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.

公开(公告)号：US20170345484A1

公开(公告)日：2017-11-30

申请号：US15678436

申请日：2017-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUYEON DOO ,  Taeyoung Oh ,  Namjong Kim ,  Chulsung Park

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/406

Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.

公开(公告)号：US20170294216A1

公开(公告)日：2017-10-12

申请号：US15416140

申请日：2017-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Taeyoung Oh

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/32

CPC classification number: G11C5/148 ,  G06F1/266 ,  G06F1/3287 ,  G06F1/3296

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.

公开(公告)号：US09767883B2

公开(公告)日：2017-09-19

申请号：US14827686

申请日：2015-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyeon Doo ,  Taeyoung Oh ,  Namjong Kim ,  Chulsung Park

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/406

Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.