公开(公告)号：US10666467B2

公开(公告)日：2020-05-26

申请号：US16108894

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye Jung Kwon ,  Seungjun Bae ,  Yongjae Lee ,  Young-Sik Kim ,  Young-Ju Kim ,  Suyeon Doo ,  Yoon-Joo Eom

IPC: G11C7/10 ,  H04L25/02 ,  G11C13/00 ,  G11C16/26 ,  G11C11/16

Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.

公开(公告)号：US20190158320A1

公开(公告)日：2019-05-23

申请号：US16108894

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye Jung Kwon ,  Seungjun Bae ,  Yongjae Lee ,  Young-Sik Kim ,  Young-Ju Kim ,  Suyeon Doo ,  Yoon-Joo Eom

IPC: H04L25/02 ,  G11C13/00 ,  G11C11/16 ,  G11C16/26

Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.

公开(公告)号：US10090039B2

公开(公告)日：2018-10-02

申请号：US15678436

申请日：2017-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyeon Doo ,  Taeyoung Oh ,  Namjong Kim ,  Chulsung Park

IPC: G11C11/406 ,  G11C7/04

Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.

公开(公告)号：US09767883B2

公开(公告)日：2017-09-19

申请号：US14827686

申请日：2015-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyeon Doo ,  Taeyoung Oh ,  Namjong Kim ,  Chulsung Park

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/406

Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.