公开(公告)号：US20220011935A1

公开(公告)日：2022-01-13

申请号：US16927798

申请日：2020-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F3/06

Abstract: A method includes sending, from an application layer, a chunk size setting to an erasure coding layer. The method further includes receiving, at the application layer, user data. The method further includes aligning, at the application layer, the user data based on the chunk size setting. The method further includes sending the aligned user data to the erasure coding layer. The method further includes partitioning, at the erasure coding layer, the aligned user data into a first data chunk and a second data chunk. The method further includes generating, at the erasure coding layer, a parity chunk based on the first data chunk and the second data chunk. The method further includes sending, from the erasure coding layer, the first data chunk, the second data chunk, and the parity chunk to a storage system.

公开(公告)号：US20190377637A1

公开(公告)日：2019-12-12

申请号：US16103907

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F11/10 ,  G06F3/06

Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

公开(公告)号：US20250021378A1

公开(公告)日：2025-01-16

申请号：US18765214

申请日：2024-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Xueyang LIU ,  Jing YANG ,  Rekha PITCHUMANI ,  Sahand SALAMAT ,  Joseph FINDLEY

IPC: G06F9/48 ,  G06F11/34

Abstract: A method may include determining, by at least one processing circuit, a first performance, on a first computational device, of a compute task, determining, by the at least one processing circuit, a second performance, on a second computational device, of the compute task, and assigning, by the at least one processing circuit, based on the first performance and the second performance, to the first computational device, the compute task. The determining the first performance may be based on a data transfer associated with the compute task. A method may include determining a characteristic of a compute task, determining a first configuration of a first computational device, determining a second configuration of a second computational device, and assigning, based on the characteristic of the compute task, the first configuration of the first computational device, and the second configuration of the second computational device, the compute task to the first computational device.

公开(公告)号：US20240403241A1

公开(公告)日：2024-12-05

申请号：US18630988

申请日：2024-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zongwang LI ,  Tong ZHANG ,  Rekha PITCHUMANI

IPC: G06F13/16 ,  G06F13/18

Abstract: A device may include a storage medium, a cache medium, a buffer medium, and at least one control circuit configured to perform one or more operations including receiving a first request to access the storage medium, accessing, based on the first request, the cache medium, copying, from a portion of the storage medium to the buffer medium, data, modifying, based on the copying, an availability of the at least a portion of the storage medium, receiving a second request to access the storage medium, and accessing, based on the second request, the buffer medium. The one or more operations may include determining a location of data associated with the second request, and accessing, based on the determining, the buffer medium. The one or more operations may include receiving information about a location of data associated with the second request, and accessing, based on the information, the buffer medium.

公开(公告)号：US20240402924A1

公开(公告)日：2024-12-05

申请号：US18418066

申请日：2024-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zongwang LI ,  Tong ZHANG ,  Rekha PITCHUMANI

IPC: G06F3/06

Abstract: A device may include a first memory media, a second memory media, and at least one control circuit configured to receive placement information for data, store, in a portion of the first memory media, based on the placement information, the data, and store, in a portion of the second memory media, based on the placement information, the data. The at least one control circuit may be configured to receive a request to access, from the portion of the first memory media, the data, and access, based on the request, from the portion of the second memory media, the data. The at least one control circuit may be configured to modify, based on an allocation status, the portion of the first memory media to an available state.

公开(公告)号：US20240345923A1

公开(公告)日：2024-10-17

申请号：US18616160

申请日：2024-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673

Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

公开(公告)号：US20240134801A1

公开(公告)日：2024-04-25

申请号：US18080211

申请日：2022-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Marie Mai NGUYEN ,  Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F12/0882 ,  G06F12/02 ,  G06F12/0891

CPC classification number: G06F12/0882 ,  G06F12/0246 ,  G06F12/0891

Abstract: Methods and memory devices are provided. A request is received from a host device at a memory device in a first state. In case that the request is a read request, first data is read from a cache of the memory device based on the read request, and the first data is output to the host device. The cache is loaded with data with the memory device in a second state. In case that the request is a write request, a block of the cache is modified to remove cache data, the cache data and corresponding data from the cache are written to a flash memory of the memory device, and second data is written to the block of the cache based on the received write request.

公开(公告)号：US20240134796A1

公开(公告)日：2024-04-25

申请号：US18163208

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shuyi PEI ,  Jing YANG ,  Rekha PITCHUMANI

IPC: G06F12/0831 ,  G06F12/0888 ,  G06F12/0891

CPC classification number: G06F12/0833 ,  G06F12/0888 ,  G06F12/0891

Abstract: Systems and methods for persistent storage with a dual interface. In some embodiments, a persistent storage device includes: a processing circuit; a cache; and persistent storage. The processing circuit may be configured to perform a method, the method including: receiving a first write request according to a first protocol; saving a data payload of the first write request in a first portion of the cache; receiving a second write request according to a second protocol; and saving a data payload of the second write request in a second portion of the cache.

公开(公告)号：US20230409245A1

公开(公告)日：2023-12-21

申请号：US17885756

申请日：2022-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heekwon PARK ,  Tong ZHANG ,  Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F3/06

CPC classification number: G06F3/0688 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0604

Abstract: A method and redundant array of independent disks (RAID) system are provided. An operation is received from an application at a file system (FS) of the RAID system. A memory mapping module of the RAID system receives at least an FS logical block address (LBA) in accordance with the operation. The memory mapping module creates a mapping from a virtual memory of the application to a RAID array in a system memory of the RAID system using at least the FS LBA.

公开(公告)号：US20230185739A1

公开(公告)日：2023-06-15

申请号：US17586767

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Marie Mai NGUYEN ,  Rekha PITCHUMANI ,  Zongwang LI ,  Yang Seok KI ,  Krishna Teja MALLADI

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: An accelerator is disclosed. A circuit may process a data to produce a processed data. A first tier storage may include a first capacity and a first latency. A second tier storage may include a second capacity and a second latency. The second capacity may be larger than the first capacity, and the second latency may be slower than the first latency. A bus may be used to transfer at least one of the data or the processed data between the first tier storage and the second tier storage.