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    TIME DOMAIN ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD
    33.
    发明公开
    TIME DOMAIN ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD 审中-公开

    公开(公告)号：US20240178857A1

    公开(公告)日：2024-05-30

    申请号：US18335572

    申请日：2023-06-15

    Applicant: Samsung Electronics Co., Ltd ,  Korea University Research and Business Foundation

    Inventor： Jihwan HYUN ,  Chulwoo KIM ,  Sooho PARK ,  Junghwan CHOI

    IPC: H03M1/38 ,  H03M1/12

    CPC classification number: H03M1/38 ,  H03M1/1245

    Abstract: In analog-to-digital conversion, a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuit configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.

    TRANSMITTER AND RECEIVER FOR 3-LEVEL PULSE AMPLITUDE MODULATION SIGNALING AND SYSTEM INCLUDING THE SAME
    34.
    发明公开
    TRANSMITTER AND RECEIVER FOR 3-LEVEL PULSE AMPLITUDE MODULATION SIGNALING AND SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230344444A1

    公开(公告)日：2023-10-26

    申请号：US17975034

    申请日：2022-10-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu SEOL ,  Sungrae KIM ,  Chisung OH ,  Junghwan CHOI

    IPC: H03M5/14 ,  H04L1/00

    CPC classification number: H03M5/145 ,  H04L1/0009 ,  H04L1/0014

    Abstract: A transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group.

    RECEIVER WITH PIPELINE STRUCTURE FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME
    36.
    发明申请
    RECEIVER WITH PIPELINE STRUCTURE FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230116188A1

    公开(公告)日：2023-04-13

    申请号：US17943448

    申请日：2022-09-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsub RIE ,  Eunseok SHIN ,  Youngdon CHOI ,  Changsoo YOON ,  Hyunyoon CHO ,  Junghwan CHOI

    IPC: G11C11/4096 ,  H03M1/12

    Abstract: A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.

    OPERATIONAL TRANSCONDUCTANCE AMPLIFIER CIRCUIT INCLUDING ACTIVE INDUCTOR
    38.
    发明申请
    OPERATIONAL TRANSCONDUCTANCE AMPLIFIER CIRCUIT INCLUDING ACTIVE INDUCTOR 有权

    公开(公告)号：US20220209729A1

    公开(公告)日：2022-06-30

    申请号：US17536064

    申请日：2021-11-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Baekjin LIM ,  Youngchul CHO ,  Seungjin PARK ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: H03F3/45

    Abstract: An amplifier circuit comprises a first unit circuit and a second unit circuit. The first unit circuit may include a first current mirror circuit that includes a first active inductor including a P-channel transistor, and a first input circuit configured to generate a first differential current and a second differential current based on a pair of differential input signals. The second unit circuit may include a second current mirror circuit that includes a second active inductor including a P-channel transistor, and a second input circuit configured to generate a third differential current and a fourth differential current based on the pair of differential input signals.

    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    39.
    发明申请
    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20220121582A1

    公开(公告)日：2022-04-21

    申请号：US17326513

    申请日：2021-05-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

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