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    SEMICONDUCTOR MEMORY DEVICE
    31.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20240422963A1

    公开(公告)日：2024-12-19

    申请号：US18604584

    申请日：2024-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KYO-SUK CHAE ,  Tai Uk Rim ,  Jin-seong Lee ,  Hee Jae Choi ,  Jung-Hoon Han ,  Byung Ha Kang ,  Gyu Taek Shin ,  Shin Woo Jeong

    IPC: H10B12/00

    Abstract: A semiconductor memory device includes a substrate including a device isolation film defining active regions; and cell gate structures in trenches, including first areas and second areas, the cell gate structures extending to intersect the active regions, each of the cell gate structures includes a cell gate insulating layer, extending along inner sidewalls of the trenches, a first gate dielectric film, on sidewalls of the cell gate insulating layer, in a first area of the trench, a second gate dielectric film, on the sidewalls of the cell gate insulating layer, in a second area of the trench, and a cell gate electrode structure, including a first gate electrode layer on sidewalls of the first gate dielectric film and a second gate electrode layer on sidewalls of the second gate dielectric film in the second area.

    Semiconductor memory device and method for fabricating the same
    33.
    发明授权
    Semiconductor memory device and method for fabricating the same 有权

    公开(公告)号：US11882688B2

    公开(公告)日：2024-01-23

    申请号：US17403984

    申请日：2021-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Hoon Han ,  Je Min Park

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34

    Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

    Semiconductor device
    34.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11843039B2

    公开(公告)日：2023-12-12

    申请号：US18074125

    申请日：2022-12-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Doosan Back ,  Dongoh Kim ,  Gyuhyun Kil ,  Jung-Hoon Han

    IPC: H01L29/423 ,  H01L29/417 ,  H01L29/51

    CPC classification number: H01L29/42368 ,  H01L29/41725 ,  H01L29/513

    Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

    Semiconductor devices having through electrodes and methods for fabricating the same
    37.
    发明授权
    Semiconductor devices having through electrodes and methods for fabricating the same 有权

    公开(公告)号：US11469157B2

    公开(公告)日：2022-10-11

    申请号：US17152012

    申请日：2021-01-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Wan Kim ,  Jung-Hoon Han ,  Dong-Sik Park

    IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768

    Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    38.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20220189962A1

    公开(公告)日：2022-06-16

    申请号：US17403984

    申请日：2021-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Hoon Han ,  Je Min Park

    IPC: H01L27/108

    Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

    Semiconductor devices having through electrodes and methods for fabricating the same
    39.
    发明授权
    Semiconductor devices having through electrodes and methods for fabricating the same 有权

    公开(公告)号：US10340204B2

    公开(公告)日：2019-07-02

    申请号：US15443259

    申请日：2017-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Wan Kim ,  Jung-Hoon Han ,  Dong-Sik Park

    IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768

    Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

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