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公开(公告)号：US20210111685A1
公开(公告)日：2021-04-15
申请号：US17064509
申请日：2020-10-06
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung LEE , Rimal Deep Singh , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Bipul Agarwal , Aravind Kumar Padyana
Abstract: Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths to provide variable gain for individual amplifier inputs. The variable gain for an individual input is provided using an amplification stage that is common for each input of the amplifier. A variable attenuation is provided for individual inputs through a combination of a band selection switch and an attenuation selection branch. Individual inputs can be configured to bypass the variable attenuation in a high gain mode.
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32.发明申请公开(公告)号：US20210111675A1
公开(公告)日：2021-04-15
申请号：US17021976
申请日：2020-09-15
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
IPC: H03F1/02 , H03F3/19 , H03F1/56 , H03G3/30 , H03F1/22 , H03F1/32 , H03F3/193 , H03F3/72 , H03G1/00 , H03G5/28
Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores in a particular gain mode to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a low noise figure amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity. The disclosed signal amplifiers can switch between a first active core and a second active core for a single or particular gain mode to achieve desired signal characteristics during different time periods.
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公开(公告)号：US10230417B2
公开(公告)日：2019-03-12
申请号：US15690947
申请日：2017-08-30
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.
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Patent Agency Ranking
公开(公告)号：US20180175797A1
公开(公告)日：2018-06-21
申请号：US15849434
申请日：2017-12-20
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
CPC classification number: H03F1/0205 , H03F1/223 , H03F1/3205 , H03F1/56 , H03F1/565 , H03F3/19 , H03F3/193 , H03F3/72 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03G1/0029 , H03G1/0088 , H03G3/3036 , H03G5/28 , H04B1/3827
Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers can also have switchable reference biases to provide targeted bias current matching. The disclosed signal amplifiers can also include degeneration switching blocks for individual amplifier cores to improve signal linearity.
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公开(公告)号：US20180034445A1
公开(公告)日：2018-02-01
申请号：US15678967
申请日：2017-08-16
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC classification number: H03H11/245 , H03H11/24 , H04M1/0277
Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.
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公开(公告)号：US09787285B2
公开(公告)日：2017-10-10
申请号：US15265160
申请日：2016-09-14
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC classification number: H03H11/245 , H03H11/24 , H04M1/0277
Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.
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37.发明申请APPARATUS AND METHODS FOR DIGITAL STEP ATTENUATORS WITH SMALL OUTPUT GLITCH 有权具有小输出玻璃的数字步进衰减器的装置和方法公开(公告)号：US20170033771A1
公开(公告)日：2017-02-02
申请号：US15265160
申请日：2016-09-14
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC classification number: H03H11/245 , H03H11/24 , H04M1/0277
Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.
Abstract translation: 本文提供了用于数字步进衰减器的装置和方法。 在某些配置中，DSA包括可以使用多个开关电路在衰减模式或旁路模式中设置的多个DSA级。 多个开关电路的第一开关电路包括场效应晶体管（FET）开关，栅极电阻，一个或多个栅极电阻旁路开关和脉冲发生电路。 栅极电阻器电连接在开关控制输入端和FET开关的栅极之间，开关控制信号可以提供给开关控制输入端以接通或关断FET开关。 响应于检测开关控制信号的上升沿和/或下降沿，脉冲发生电路可以控制一个或多个栅极电阻旁路开关绕过栅极电阻。
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38.发明申请APPARATUS AND METHODS FOR DIGITAL STEP ATTENUATORS WITH SMALL OUTPUT GLITCH 有权具有小输出玻璃的数字步进衰减器的装置和方法公开(公告)号：US20150326204A1
公开(公告)日：2015-11-12
申请号：US14704199
申请日：2015-05-05
Applicant: Skyworks Solutions, Inc.
Inventor： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
IPC: H03H11/24
CPC classification number: H03H11/245 , H03H11/24 , H04M1/0277
Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.
Abstract translation: 本文提供了用于数字步进衰减器的装置和方法。 在某些配置中，DSA包括可以使用多个开关电路在衰减模式或旁路模式中设置的多个DSA级。 多个开关电路的第一开关电路包括场效应晶体管（FET）开关，栅极电阻，一个或多个栅极电阻旁路开关和脉冲发生电路。 栅极电阻器电连接在开关控制输入端和FET开关的栅极之间，开关控制信号可以提供给开关控制输入端以接通或关断FET开关。 响应于检测开关控制信号的上升沿和/或下降沿，脉冲发生电路可以控制一个或多个栅极电阻旁路开关绕过栅极电阻。
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