知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

38 条记录 (耗时 0.024 秒)

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    32.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210399008A1

    公开(公告)日：2021-12-23

    申请号：US17154159

    申请日：2021-01-21

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Ju-Young LIM ,  Jongsoo KIM ,  Jesuk MOON ,  Dongwoo KIM ,  Sunil SHIM ,  Wonseok CHO

    IPC分类号： H01L27/11582 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11526

    摘要： A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.

    SEMICONDUCTOR DEVICE AND A DATA STORAGE SYSTEM INCLUDING THE SAME
    36.
    发明申请
    SEMICONDUCTOR DEVICE AND A DATA STORAGE SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220254807A1

    公开(公告)日：2022-08-11

    申请号：US17507929

    申请日：2021-10-22

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jongsoo KIM ,  Sunil Shim ,  Juyoung Lim ,  Wonseok Cho

    IPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

    摘要： A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level.