公开(公告)号：US20230015172A1

公开(公告)日：2023-01-19

申请号：US17952699

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Jinseong HEO ,  Sangwook KIM ,  Yunseong LEE

IPC: H01L49/02 ,  H01L51/05 ,  H01L29/78 ,  H01L21/02 ,  H01L29/40 ,  H01L27/11507 ,  H01L27/1159 ,  H01L29/49

Abstract: Disclosed are a thin film structure and an electronic device including the same. The disclosed thin film structure includes a dielectric material layer between a first material layer and a second material layer. The dielectric material layer includes a dopant in a matrix material having a fluorite structure. The dielectric material layer is uniformly doped with a low concentration of the dopant, and has ferroelectricity.

公开(公告)号：US20220384656A1

公开(公告)日：2022-12-01

申请号：US17540607

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

公开(公告)号：US20220173099A1

公开(公告)日：2022-06-02

申请号：US17491841

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Seunggeol NAM ,  Taehwan MOON ,  Kwanghee LEE ,  Jinseong HEO ,  Hagyoul BAE ,  Yunseong LEE

IPC: H01L27/092 ,  H01L27/11 ,  H01L29/24 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

Abstract: Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

公开(公告)号：US20220140148A1

公开(公告)日：2022-05-05

申请号：US17515984

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Jinseong HEO ,  Sangwook KIM ,  Hagyoul BAE ,  Taehwan MOON ,  Yunseong LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/51

Abstract: Provided is a ferroelectric semiconductor device including a source and a drain having different polarities. The ferroelectric semiconductor may include a ferroelectric including zirconium oxide (ZrO2), hafnium oxide (HfO2), and/or hafnium-zirconium oxide (HfxZr1−xO, 0

公开(公告)号：US20210117604A1

公开(公告)日：2021-04-22

申请号：US16856216

申请日：2020-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyubin HAN ,  Sangwook KIM

IPC: G06F30/392 ,  H01L21/033

Abstract: A layout of original pattern is rotated in a rotational direction to form a layout of rotation pattern. Vertices and segment points of the layout of rotation pattern are matched with ones of the reference points closest thereto, and the matched reference points are connected to form a layout of first modification pattern. A region of the layout of first modification pattern is enlarged to form a layout of second modification pattern. A layout of reference pattern having the same direction as the layout of rotation pattern is formed. A layout of target pattern is formed based on a region where the layouts of reference pattern and second modification pattern overlap. An optical proximity correction is performed on the layout of target pattern to form a layout of third modification pattern, which is rotated in a reverse rotational direction to form a layout of final pattern.

公开(公告)号：US20210098595A1

公开(公告)日：2021-04-01

申请号：US16890231

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Sangwook KIM ,  Sanghyun JO ,  Jinseong HEO ,  Hyangsook LEE

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02

Abstract: A ferroelectric thin-film structure includes at least one first atomic layer and at least one second atomic layer. The first atomic layer includes a first dielectric material that is based on an oxide, and the second atomic layer includes both the first dielectric material and a dopant that has a bandgap greater than a bandgap of the dielectric material.

公开(公告)号：US20190354843A1

公开(公告)日：2019-11-21

申请号：US16414257

申请日：2019-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaechul PARK ,  Sangwook KIM

IPC: G06N3/063 ,  G11C13/00 ,  H01L25/065

Abstract: A neuromorphic apparatus includes a three-dimensionally-stacked synaptic structure, and includes a plurality of unit synaptic modules, each of the plurality of unit synaptic modules including a plurality of synaptic layers, each of the plurality of synaptic layers including a plurality of stacked layers, and each of the plurality of unit synaptic modules further including a first decoder interposed between two among the plurality of synaptic layers. The neuromorphic apparatus further includes a second decoder that provides a level selection signal to the first decoder included in one among the plurality of unit synaptic modules to be accessed, and a third decoder that generates an address of one among a plurality of memristers to be accessed in a memrister array of one among the plurality of synaptic layers included in the one among the plurality of unit synaptic modules to be accessed.

公开(公告)号：US20150279669A1

公开(公告)日：2015-10-01

申请号：US14537207

申请日：2014-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION

Inventor： Kyunghoon CHO ,  Sangwook KIM ,  Donghyeok CHOI

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/24

CPC classification number: H01L21/02565 ,  B82Y10/00 ,  H01L21/02422 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02614 ,  H01L21/02628 ,  H01L29/0673 ,  H01L29/24

Abstract: A method of preparing a ZnO nanowire, and a ZnO nanowire prepared by the method are provided. The method of preparing a ZnO nanowire includes: preparing a zinc chalcogenide solution by dissolving zinc chalcogenide in a solvent; applying the zinc chalcogenide solution onto a substrate; drying the zinc chalcogenide solution applied onto the substrate; and annealing the substrate in the presence of oxygen after the drying the zinc chalcogenide solution.

Abstract translation: 提供了制备ZnO纳米线的方法和通过该方法制备的ZnO纳米线。 制备ZnO纳米线的方法包括：通过将硫属化合物溶解在溶剂中来制备硫属化合物溶液; 将锌硫属化物溶液施加到基底上; 干燥施加到基底上的硫属化合物溶液; 并在干燥锌硫属化物溶液之后在氧气存在下退火底物。

公开(公告)号：US20250072055A1

公开(公告)日：2025-02-27

申请号：US18944685

申请日：2024-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

公开(公告)号：US20240234557A1

公开(公告)日：2024-07-11

申请号：US18515102

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Jeeeun YANG ,  Sangwook KIM ,  Kyung-Eun BYUN ,  Eunkyu LEE

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L29/24 ,  H01L29/4236 ,  H01L29/66969

Abstract: Disclosed are a semiconductor device, a method of manufacturing the same, and an electronic element and an electronic apparatus each including the semiconductor device. The semiconductor device may include a substrate, a channel layer on the substrate, a first electrode and a second electrode on two opposite ends of the channel layer, respectively, and spaced apart from each other, a gate electrode on the channel layer and spaced apart from the first electrode and the second electrode, a gate dielectric material provided between the channel layer and the gate electrode, and a chalcogen compound layer being at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer.