公开(公告)号：US06579157B1

公开(公告)日：2003-06-17

申请号：US09823788

申请日：2001-03-30

Applicant: Yehiel Gotkis ,  Aleksander A. Owczarz ,  Rodney Kistler

Inventor： Yehiel Gotkis ,  Aleksander A. Owczarz ,  Rodney Kistler

IPC: B24B100

CPC classification number: B24B53/017 ,  B24B21/04

Abstract: A method for smoothing a surface of a polishing pad previously used in planarizing a surface of a substrate in a chemical mechanical planarization (CMP) system is provided. The method starts by conditioning the surface of the polishing pad so as to create a post-conditioned surface having a plurality of asperities. The post-conditioned surface of the polishing pad is then ironed, thus compressing the plurality of asperities onto the post-conditioned surface of the polishing pad such that the plurality of asperities lay substantially flat against the post-conditioned surface of the polishing pad.

Abstract translation: 提供了一种用于平滑化学机械平面化（CMP）系统中用于平坦化基板表面的抛光垫表面的方法。 该方法通过调节抛光垫的表面开始，以便产生具有多个凹凸的后处理表面。 然后熨烫抛光垫的后处理表面，从而将多个凹凸压缩到抛光垫的后处理表面上，使得多个凹凸基本上平坦地抵靠抛光垫的后处理表面。

公开(公告)号：US08427185B2

公开(公告)日：2013-04-23

申请号：US13024379

申请日：2011-02-10

Applicant: George H. Zapalac, Jr. ,  Kirk J. Bertsche ,  David L. Brown ,  J. Kirkwood H. Rough ,  David A. Soltz ,  Yehiel Gotkis

Inventor： George H. Zapalac, Jr. ,  Kirk J. Bertsche ,  David L. Brown ,  J. Kirkwood H. Rough ,  David A. Soltz ,  Yehiel Gotkis

IPC: G01R31/308 ,  G01R31/08

CPC classification number: H02S50/10

Abstract: A method of inline inspection of photovoltaic material for electrical anomalies. A first electrical connection is formed to a first surface of the photovoltaic material, and a second electrical connection is formed to an opposing second surface of the photovoltaic material. A localized current is induced in the photovoltaic material and properties of the localized current in the photovoltaic material are sensed using the first and second electrical connections. The properties of the sensed localized current are analyzed to detect the electrical anomalies in the photovoltaic material.

Abstract translation: 一种用于电气异常的光伏材料的在线检查方法。 第一电连接形成在光伏材料的第一表面上，并且第二电连接形成在光伏材料的相对的第二表面上。 在光伏材料中感应到局部电流，并且使用第一和第二电连接来感测光伏材料中局部电流的特性。 分析感测到的局部电流的性质以检测光伏材料中的电气异常。

公开(公告)号：US20130056038A1

公开(公告)日：2013-03-07

申请号：US13530107

申请日：2012-06-22

Applicant: Yehiel Gotkis

Inventor： Yehiel Gotkis

IPC: B08B3/10

CPC classification number: B08B3/102 ,  H01L21/02057

Abstract: A method controllably and sustainably creates an upwardly directed gradient of dropping temperatures in a wet treatment tank between a cooled and face down workpiece (e.g., an in-process semiconductor wafer) and a lower down heat source. A thermal fluid upwell containing thermally collapsible bubbles is then directed from the heat source to the face down workpiece. In one class of embodiments, bubble collapse energy release and/or bubble collapse locations are controlled so as to avoid exposing delicate features of the to-be-treated surface to damaging forces. In one class of embodiments the wet treatment includes ultra-cleaning of the work face. Cleaning fluids that are essentially free of predefined contaminates are upwelled to the to-be-cleaned surface and potentially contaminated after-flows are convectively directed away from the workpiece so as to prevent recontamination of the workpiece.

Abstract translation: 方法可控地和可持续地产生在冷处理槽中的向上倾斜的温度梯度，所述湿处理槽在冷却和向下工件（例如，在工艺中的半导体晶片）和较低的下热源之间。 然后将含有热可收缩气泡的热流体上部井从热源引导到工件的正面。 在一类实施例中，控制气泡塌陷能量释放和/或气泡塌陷位置，以避免将被处理表面的微妙特征暴露于破坏力。 在一类实施例中，湿处理包括工作面的超清洁。 基本上没有预定污染物的清洁液体被上浮到待清洁的表面，并且可能被污染的后流动物被对流地远离工件，以防止工件的再污染。

公开(公告)号：US07875548B2

公开(公告)日：2011-01-25

申请号：US12188145

申请日：2008-08-07

Applicant: Yehiel Gotkis ,  David Wei ,  Rodney Kistler

Inventor： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

IPC: H01L21/4763

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

Abstract translation: 提供了在其上形成有晶体管的衬底上制造半导体结构的方法。 一种方法包括形成多个级别的互连金属化结构。 互连金属化结构的形成包括沉积牺牲层并执行将沟槽，通路和短截线蚀刻到牺牲层中的工艺。 该方法还包括填充和平坦化被蚀刻的沟槽，通路和短截线，然后在互连金属化结构的整个层级上蚀刻除去牺牲层。 蚀刻留下空隙互连金属化结构，其结构上由非电功能的短截线支撑。

公开(公告)号：US20090004845A1

公开(公告)日：2009-01-01

申请号：US12188145

申请日：2008-08-07

Applicant: Yehiel Gotkis ,  David Wei ,  Rodney Kistler

Inventor： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

IPC: H01L21/4763

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

Abstract translation: 提供了在其上形成有晶体管的衬底上制造半导体结构的方法。 一种方法包括形成多个级别的互连金属化结构。 互连金属化结构的形成包括沉积牺牲层并执行将沟槽，通路和短截线蚀刻到牺牲层中的工艺。 该方法还包括填充和平坦化被蚀刻的沟槽，通路和短截线，然后在互连金属化结构的整个层级上蚀刻除去牺牲层。 蚀刻留下空隙互连金属化结构，其结构上由非电功能的短截线支撑。

公开(公告)号：US20080190459A1

公开(公告)日：2008-08-14

申请号：US12027724

申请日：2008-02-07

Applicant: Yehiel Gotkis

Inventor： Yehiel Gotkis

IPC: B08B3/10 ,  B08B5/00 ,  B08B11/00

CPC classification number: B08B3/102 ,  H01L21/02057

Abstract: An upwardly directed gradient of dropping temperatures is controllably and sustainably created in a wet treatment tank between a cooled and face down workpiece (e.g., an in-process semiconductor wafer) and a lower down heat source. A thermal fluid upwell containing thermally collapsible bubbles is directed from the heat source to the face down workpiece. In one class of embodiments, bubble collapse energies and/or bubble collapse locations are controlled so as to avoid exposing delicate features of the to-be-treated surface to damaging forces. For example, rapid collapse of the thermally collapsible bubbles is caused to occur at a predefined safe distance away from the delicate work face of the workpiece so that the delicate work face is not damaged and yet treatment effective kinetic energies are coupled from the collapsing bubbles to the work face. In one class of embodiments the wet treatment includes ultracleaning of the work face. Cleaning fluids that are essentially free of predefined contaminates are upwelled to the to-be-cleaned surface and potentially contaminated after-flows are convectively directed away from the workpiece so as to prevent recontamination of the workpiece.

Abstract translation: 在冷却和正面朝下的工件（例如，在工艺中的半导体晶片）和较低的下热源之间的湿处理槽中可控地和可持续地产生向上的降落温度梯度。 包含热可折叠气泡的热流体上部空间从热源引导到工件的正面。 在一类实施例中，控制气泡塌陷能量和/或气泡塌陷位置，以避免将被处理表面的微妙特征暴露于破坏力。 例如，热可折叠气泡的快速塌陷在远离工件的精细工作面的预定安全距离处发生，使得精细的工作面不被损坏，并且处理有效的动能从塌陷气泡耦合到 工作面。 在一类实施方案中，湿处理包括工作面的超级清洁。 基本上没有预定污染物的清洁液体被上浮到待清洁的表面，并且可能被污染的后流动物被对流地远离工件，以防止工件的再污染。

公开(公告)号：US07205166B2

公开(公告)日：2007-04-17

申请号：US10749531

申请日：2003-12-30

Applicant: Yehiel Gotkis ,  Rodney Kistler ,  Aleksander Owczarz ,  Charles Freund

Inventor： Yehiel Gotkis ,  Rodney Kistler ,  Aleksander Owczarz ,  Charles Freund

IPC: H01L21/66

CPC classification number: G01B7/107 ,  G01B7/105 ,  G01B2210/44

Abstract: A method for minimizing measuring spot size and noise during film thickness measurement is provided. The method initiates with locating a first eddy current sensor directed toward a first surface associated with a conductive film. The method includes locating a second eddy current sensor directed toward a second surface associated with the conductive film. The first and second eddy current sensors may share a common axis or be offset from each other. The method further includes alternating power supplied to the first eddy current sensor and the second eddy current sensor, such that the first eddy current sensor and the second eddy current sensor are powered one at a time. In one aspect of the invention, a delay time is incorporated between switching power between the first eddy current sensor and the second eddy current sensor. The method also includes calculating the film thickness measurement based on a combination of signals from the first eddy current sensor and the second eddy current sensor. An apparatus and a system are also provided.

Abstract translation: 提供了一种在膜厚测量期间最小化测量点尺寸和噪声的方法。 该方法通过定位朝向与导电膜相关联的第一表面的第一涡流传感器来启动。 该方法包括定位朝向与导电膜相关联的第二表面的第二涡流传感器。 第一和第二涡流传感器可以共享公共轴线或彼此偏移。 该方法还包括供应给第一涡流传感器和第二涡流传感器的交流电力，使得第一涡流传感器和第二涡流传感器一次一个地供电。 在本发明的一个方面，在第一涡流传感器和第二涡流传感器之间的开关功率之间并入延迟时间。 该方法还包括基于来自第一涡流传感器和第二涡流传感器的信号的组合来计算膜厚度测量。 还提供了一种装置和系统。

公开(公告)号：US07128803B2

公开(公告)日：2006-10-31

申请号：US10186472

申请日：2002-06-28

Applicant: Aleksander Owczarz ,  Yehiel Gotkis ,  Dave Hemker ,  Rodney Kistler

Inventor： Aleksander Owczarz ,  Yehiel Gotkis ,  Dave Hemker ,  Rodney Kistler

IPC: C23F1/00 ,  H01L21/306

CPC classification number: B24B1/005 ,  B24B37/013 ,  B24B49/105 ,  B24B57/02 ,  H01L21/67253

Abstract: A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A cluster of sensors external to the CMP tool is included. The cluster of sensors is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The cluster of sensors provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.

Abstract translation: 提供了一种用于处理晶片的系统。 该系统包括化学机械平面化（CMP）工具。 CMP工具包括限定在壳体内的晶片载体。 载体膜固定到底表面并支撑晶片。 嵌入晶片载体的传感器。 传感器被配置为在晶片中感应涡流以确定晶片的接近度和厚度。 包括CMP工具外部的一组传感器。 传感器组与嵌入晶片载体中的传感器进行通信，并且基本上消除了距离灵敏度。 传感器簇提供晶片的初始厚度，以允许对嵌入在晶片载体中的传感器执行校准。 校准偏移了在CMP操作期间确定晶片厚度的不准确性的变量。 还提供了一种方法和装置。

公开(公告)号：US07010468B2

公开(公告)日：2006-03-07

申请号：US11030374

申请日：2005-01-05

Applicant: Yehiel Gotkis ,  Vladimir Katz ,  David Hemker ,  Rodney Kistler ,  Nicolas J. Bright

Inventor： Yehiel Gotkis ,  Vladimir Katz ,  David Hemker ,  Rodney Kistler ,  Nicolas J. Bright

IPC: H04B15/00

CPC classification number: G05B23/0254 ,  H01L22/26

Abstract: A method for converting a slope based detection task to a threshold based detection task is provided. The method initiates with defining an approximation equation for a set of points corresponding to values of a process being monitored. Then, an expected value at a current point of the process being monitored is predicted. Next, a difference between a measured value at the current point of the process being monitored and the corresponding expected value is calculated. Then, the difference is monitored for successive points to detect a deviation value between the measured value and the expected value. Next, a transition point for the process being monitored is identified based on the detection of the deviation value. A processing system configured to provide real time data for a slope based transition and a computer readable media are also provided.

Abstract translation: 提供了一种将基于斜率的检测任务转换为基于阈值的检测任务的方法。 该方法通过为对应于被监视的进程的值的一组点定义近似方程来启动。 然后，预测在被监视的处理的当前点的期望值。 接下来，计算被监视处理的当前点的测量值与对应的期望值之间的差。 然后，对连续点监测差异，以检测测量值和预期值之间的偏差值。 接下来，基于偏差值的检测来识别被监视处理的转变点。 还提供了一种处理系统，其被配置为提供用于基于斜率的转换的实时数据和计算机可读介质。

公开(公告)号：US20050194688A1

公开(公告)日：2005-09-08

申请号：US09821415

申请日：2001-03-28

Applicant: Yehiel Gotkis ,  David Wei ,  Rodney Kistler

Inventor： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having transistor devices and a plurality of copper interconnect metallization lines and conductive vias. The plurality of copper interconnect metallization lines and conductive vias are defined in each of a plurality of interconnect levels of the semiconductor device such that the plurality of copper interconnect metallization lines and conductive vias are isolated from each other by an air dielectric. The semiconductor device further includes a plurality of supporting stubs each of which is configured to form a supporting column that extends through the plurality of interconnect levels of the semiconductor device.

Abstract translation: 提供半导体器件。 半导体器件包括具有晶体管器件和多个铜互连金属化线和导电通孔的衬底。 多个铜互连金属化线和导电通孔被限定在半导体器件的多个互连层中的每一个中，使得多个铜互连金属化线和导电通孔通过空气电介质彼此隔离。 半导体器件还包括多个支撑短截线，每个支撑短截线被配置成形成延伸穿过半导体器件的多个互连级别的支撑柱。