公开(公告)号：US08347040B2

公开(公告)日：2013-01-01

申请号：US13089050

申请日：2011-04-18

Applicant: Brian P. Lilly ,  Sridhar P. Subramanian ,  Ramesh Gunna

Inventor： Brian P. Lilly ,  Sridhar P. Subramanian ,  Ramesh Gunna

IPC: G06F12/00

CPC classification number: G06F12/0831 ,  G06F12/084

Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

Abstract translation: 在一个实施例中，系统包括耦合到互连的多个代理和耦合到互连的高速缓存。 多个代理被配置为高速缓存数据。 多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务，并且多个代理中的其他代理被配置为从互连窥探存储器请求。 其他代理在交互的响应阶段提供响应。 高速缓存被配置为检测存储器请求的命中，并且在响应阶段之前将事务的数据提供给第一代理，并且独立于响应。

公开(公告)号：US20120047332A1

公开(公告)日：2012-02-23

申请号：US12860505

申请日：2010-08-20

Applicant: Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

Inventor： Peter J. Bannon ,  Andrew J. Beaumont-Smith ,  Ramesh Gunna ,  Wei-han Lien ,  Brian P. Lilly ,  Jaidev P. Patwardhan ,  Shih-Chieh R. Wen ,  Tse-Yu Yeh

IPC: G06F12/08 ,  G06F3/00 ,  G06F12/00

CPC classification number: G06F12/0891 ,  G06F12/0804

Abstract: In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

Abstract translation: 在一个实施例中，组合写缓冲器被配置为维护一个或多个刷新度量以确定何时从缓冲器条目发送写入操作。 组合写缓冲器可以被配置为响应于写缓冲器中的活动来动态地修改刷新度量，修改写操作从写缓冲器发送到下一较低级存储器的条件。 例如，在一个实现中，刷新度量可以包括将写缓冲器条目分类为“折叠”。折叠的写入缓冲器条目及其中的折叠的写入操作可以包括至少一个写入操作，该写入操作已覆盖由 以前的写入操作在缓冲区条目中。 在另一实现中，组合写缓冲器可以将缓冲器充满度的阈值保持为刷新度量，并且可以基于实际的缓冲器充满度随时间调整缓冲器充满度。

公开(公告)号：US07991928B2

公开(公告)日：2011-08-02

申请号：US12408410

申请日：2009-03-20

Applicant: James B. Keller ,  Sridhar P. Subramanian ,  Ramesh Gunna

Inventor： James B. Keller ,  Sridhar P. Subramanian ,  Ramesh Gunna

IPC: G06F3/00 ,  G06F15/167

CPC classification number: G06F12/0831 ,  G06F13/362 ,  G06F13/4213 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.

Abstract translation: 接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。 在一个实施例中，控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。 控制单元被配置为记录在互连上提供的标识符，该重试响应标识互连上正在进行的第二事务。 控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。 在另一个实施例中，控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应 。 控制单元还被配置为提供具有重试响应的第二事务的标识符。

公开(公告)号：US20100235675A1

公开(公告)日：2010-09-16

申请号：US12787865

申请日：2010-05-26

Applicant: Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

Inventor： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

IPC: G06F13/14 ,  G06F1/04 ,  G06F13/362

CPC classification number: G06F13/362 ,  G06F13/4022

Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Abstract translation: 在一个实施例中，开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。 在另一个实施例中，预期了一种方法。

公开(公告)号：US20080307168A1

公开(公告)日：2008-12-11

申请号：US11758219

申请日：2007-06-05

Applicant: Brian P. Lilly ,  Sridhar P. Subramanian ,  Ramesh Gunna

Inventor： Brian P. Lilly ,  Sridhar P. Subramanian ,  Ramesh Gunna

IPC: G06F12/00

CPC classification number: G06F12/0831 ,  G06F12/084

Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

Abstract translation: 在一个实施例中，系统包括耦合到互连的多个代理和耦合到互连的高速缓存。 多个代理被配置为高速缓存数据。 多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务，并且多个代理中的其他代理被配置为从互连窥探存储器请求。 其他代理在交互的响应阶段提供响应。 高速缓存被配置为检测存储器请求的命中，并且在响应阶段之前将事务的数据提供给第一代理，并且独立于响应。

公开(公告)号：US07461190B2

公开(公告)日：2008-12-02

申请号：US11201581

申请日：2005-08-11

Applicant: Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

Inventor： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

IPC: G06F13/00

CPC classification number: G06F13/362 ,  G06F13/4022

Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Abstract translation: 在一个实施例中，开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。 在另一个实施例中，预期了一种方法。

公开(公告)号：US07398361B2

公开(公告)日：2008-07-08

申请号：US11215604

申请日：2005-08-30

Applicant: Ramesh Gunna ,  Po-Yung Chang ,  Sridhar P. Subramanian ,  James B. Keller ,  Tse-Yuh Yeh

Inventor： Ramesh Gunna ,  Po-Yung Chang ,  Sridhar P. Subramanian ,  James B. Keller ,  Tse-Yuh Yeh

IPC: G06F13/00

CPC classification number: G06F12/0831

Abstract: In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue. Responsive to a first processor core request received by the interface unit from the processor core, the control unit is configured to allocate a second address buffer entry of the address buffer to store the first processor core request and to store a second pointer to the second address buffer entry in the second queue.

Abstract translation: 在一个实施例中，接口单元包括地址缓冲器和耦合到地址缓冲器的控制单元。 地址缓冲器被配置为存储由处理器核心产生的处理器核心请求的地址和从互连接​​收的窥探请求的地址。 所述控制单元被配置为维护多个队列，其中所述多个队列中的至少第一队列专用于窥探请求，并且所述多个队列中的至少第二队列专用于处理器核心请求。 响应于接口单元从互连接收到的第一窥探请求，控制单元被配置为分配地址缓冲器的第一地址缓冲器条目以存储第一窥探请求，并且将第一指针存储到第一地址缓冲器条目中 第一个队列。 响应于接口单元从处理器核心接收到的第一处理器核心请求，控制单元被配置为分配地址缓冲器的第二地址缓冲器条目以存储第一处理器核心请求并将第二指针存储到第二地址 第二个队列中的缓冲区条目。

公开(公告)号：US08555040B2

公开(公告)日：2013-10-08

申请号：US12785939

申请日：2010-05-24

Applicant: Andrew J. Beaumont-Smith ,  Ramesh Gunna

Inventor： Andrew J. Beaumont-Smith ,  Ramesh Gunna

IPC: G06F9/32

CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/3848

Abstract: In one embodiment, a processor implements an indirect branch target predictor to predict target addresses of indirect branch instructions. The indirect branch target predictor may store target addresses generated during previous executions of indirect branches, and may use the stored target addresses as predictions for current indirect branches. The indirect branch target predictor may also store a validation tag corresponding to each stored target address. The validation tag may be compared to similar data corresponding to the current indirect branch being predicted. If the validation tag does not match, the indirect branch is presumed to be mispredicted (since the branch target address actually belongs to a different instruction). The indirect branch target predictor may inhibit speculative execution subsequent to the mispredicted indirect branch until the redirect is signalled for the mispredicted indirect branch.

Abstract translation: 在一个实施例中，处理器实现间接分支目标预测器来预测间接分支指令的目标地址。 间接分支目标预测器可以存储在先前执行间接分支期间生成的目标地址，并且可以使用存储的目标地址作为当前间接分支的预测。 间接分支目标预测器还可以存储对应于每个存储的目标地址的验证标签。 可以将验证标签与对应于正在预测的当前间接分支的类似数据进行比较。 如果验证标签不匹配，则假定间接分支被错误预测（因为分支目标地址实际上属于不同的指令）。 间接分支目标预测器可能会在误预测的间接分支之后抑制推测性执行，直到重新发送给错误的间接分支。

公开(公告)号：US08341379B2

公开(公告)日：2012-12-25

申请号：US12774389

申请日：2010-05-05

Applicant: Jesse Pan ,  Ramesh Gunna

Inventor： Jesse Pan ,  Ramesh Gunna

IPC: G06F12/00

CPC classification number: G06F12/10 ,  G06F12/1072 ,  G06F12/124

Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

Abstract translation: 在一个实施例中，处理器包括存储器管理单元（MMU）和耦合到MMU和处理器的接口单元的接口单元。 MMU包括被配置为存储未决硬件生成的页表项（PTE）更新的队列。 接口单元被配置为在接口上接收同步操作，所述同步操作被定义为使未决的硬件产生的PTE更新（如果有的话）被写入存储器。 MMU配置为接受在接收同步操作之后生成的后续硬件生成的PTE更新，即使同步操作在接口上尚未完成。 在一些实施例中，MMU可以响应于从队列发送未决PTE更新来接受后续PTE更新。 在其他实施例中，可以在队列中识别未决PTE更新，并且可以接收后续更新。

公开(公告)号：US20110289300A1

公开(公告)日：2011-11-24

申请号：US12785939

申请日：2010-05-24

Applicant: Andrew J. Beaumont-Smith ,  Ramesh Gunna

Inventor： Andrew J. Beaumont-Smith ,  Ramesh Gunna

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/3848

Abstract: In one embodiment, a processor implements an indirect branch target predictor to predict target addresses of indirect branch instructions. The indirect branch target predictor may store target addresses generated during previous executions of indirect branches, and may use the stored target addresses as predictions for current indirect branches. The indirect branch target predictor may also store a validation tag corresponding to each stored target address. The validation tag may be compared to similar data corresponding to the current indirect branch being predicted. If the validation tag does not match, the indirect branch is presumed to be mispredicted (since the branch target address actually belongs to a different instruction). The indirect branch target predictor may inhibit speculative execution subsequent to the mispredicted indirect branch until the redirect is signalled for the mispredicted indirect branch.

Abstract translation: 在一个实施例中，处理器实现间接分支目标预测器来预测间接分支指令的目标地址。 间接分支目标预测器可以存储在先前执行间接分支期间生成的目标地址，并且可以使用存储的目标地址作为当前间接分支的预测。 间接分支目标预测器还可以存储对应于每个存储的目标地址的验证标签。 可以将验证标签与对应于正在预测的当前间接分支的类似数据进行比较。 如果验证标签不匹配，则假定间接分支被错误预测（因为分支目标地址实际上属于不同的指令）。 间接分支目标预测器可能会在误预测的间接分支之后抑制推测性执行，直到重新发送给错误的间接分支。