Latency Reduction for Cache Coherent Bus-Based Cache
    1.
    发明申请
    Latency Reduction for Cache Coherent Bus-Based Cache 有权
    缓存相干总线缓存的延迟降低

    公开(公告)号:US20110197030A1

    公开(公告)日:2011-08-11

    申请号:US13089050

    申请日:2011-04-18

    CPC classification number: G06F12/0831 G06F12/084

    Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

    Abstract translation: 在一个实施例中,系统包括耦合到互连的多个代理和耦合到互连的高速缓存。 多个代理被配置为高速缓存数据。 多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务,并且多个代理中的其他代理被配置为从互连窥探存储器请求。 其他代理在交互的响应阶段提供响应。 高速缓存被配置为检测存储器请求的命中,并且在响应阶段之前将事务的数据提供给第一代理,并且独立于响应。

    Latency reduction for cache coherent bus-based cache
    2.
    发明授权
    Latency reduction for cache coherent bus-based cache 有权
    缓存相关总线缓存的延迟降低

    公开(公告)号:US07949832B2

    公开(公告)日:2011-05-24

    申请号:US12714884

    申请日:2010-03-01

    CPC classification number: G06F12/0831 G06F12/084

    Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

    Abstract translation: 在一个实施例中,系统包括耦合到互连的多个代理和耦合到互连的高速缓存。 多个代理被配置为高速缓存数据。 多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务,并且多个代理中的其他代理被配置为从互连窥探存储器请求。 其他代理在交互的响应阶段提供响应。 高速缓存被配置为检测存储器请求的命中,并且在响应阶段之前将事务的数据提供给第一代理,并且独立于响应。

    Latency Reduction for Cache Coherent Bus-Based Cache
    3.
    发明申请
    Latency Reduction for Cache Coherent Bus-Based Cache 有权
    缓存相干总线缓存的延迟降低

    公开(公告)号:US20100161905A1

    公开(公告)日:2010-06-24

    申请号:US12714884

    申请日:2010-03-01

    CPC classification number: G06F12/0831 G06F12/084

    Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

    Abstract translation: 在一个实施例中,系统包括耦合到互连的多个代理和耦合到互连的高速缓存。 多个代理被配置为高速缓存数据。 多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务,并且多个代理中的其他代理被配置为从互连窥探存储器请求。 其他代理在交互的响应阶段提供响应。 高速缓存被配置为检测存储器请求的命中,并且在响应阶段之前将事务的数据提供给第一代理,并且独立于响应。

    Latency reduction for cache coherent bus-based cache
    4.
    发明授权
    Latency reduction for cache coherent bus-based cache 有权
    缓存相关总线缓存的延迟降低

    公开(公告)号:US08347040B2

    公开(公告)日:2013-01-01

    申请号:US13089050

    申请日:2011-04-18

    CPC classification number: G06F12/0831 G06F12/084

    Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

    Abstract translation: 在一个实施例中,系统包括耦合到互连的多个代理和耦合到互连的高速缓存。 多个代理被配置为高速缓存数据。 多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务,并且多个代理中的其他代理被配置为从互连窥探存储器请求。 其他代理在交互的响应阶段提供响应。 高速缓存被配置为检测存储器请求的命中,并且在响应阶段之前将事务的数据提供给第一代理,并且独立于响应。

    Latency Reduction for Cache Coherent Bus-Based Cache
    5.
    发明申请
    Latency Reduction for Cache Coherent Bus-Based Cache 有权
    缓存相干总线缓存的延迟降低

    公开(公告)号:US20080307168A1

    公开(公告)日:2008-12-11

    申请号:US11758219

    申请日:2007-06-05

    CPC classification number: G06F12/0831 G06F12/084

    Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

    Abstract translation: 在一个实施例中,系统包括耦合到互连的多个代理和耦合到互连的高速缓存。 多个代理被配置为高速缓存数据。 多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务,并且多个代理中的其他代理被配置为从互连窥探存储器请求。 其他代理在交互的响应阶段提供响应。 高速缓存被配置为检测存储器请求的命中,并且在响应阶段之前将事务的数据提供给第一代理,并且独立于响应。

    Latency reduction for cache coherent bus-based cache
    6.
    发明授权
    Latency reduction for cache coherent bus-based cache 有权
    缓存相关总线缓存的延迟降低

    公开(公告)号:US07702858B2

    公开(公告)日:2010-04-20

    申请号:US11758219

    申请日:2007-06-05

    CPC classification number: G06F12/0831 G06F12/084

    Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

    Abstract translation: 在一个实施例中,系统包括耦合到互连的多个代理和耦合到互连的高速缓存。 多个代理被配置为高速缓存数据。 多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务,并且多个代理中的其他代理被配置为从互连窥探存储器请求。 其他代理在交互的响应阶段提供响应。 高速缓存被配置为检测存储器请求的命中,并且在响应阶段之前将事务的数据提供给第一代理,并且独立于响应。

    Retry mechanism
    7.
    发明授权
    Retry mechanism 有权
    重试机制

    公开(公告)号:US08359414B2

    公开(公告)日:2013-01-22

    申请号:US13165235

    申请日:2011-06-21

    Abstract: An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.

    Abstract translation: 接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。 在一个实施例中,控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。 控制单元被配置为记录在互连上提供的标识符,该重试响应标识互连上正在进行的第二事务。 控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。 在另一个实施例中,控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应 。 控制单元还被配置为提供具有重试响应的第二事务的标识符。

    Retry mechanism in cache coherent communication among agents
    8.
    发明授权
    Retry mechanism in cache coherent communication among agents 有权
    代理之间缓存一致通信中的重试机制

    公开(公告)号:US07529866B2

    公开(公告)日:2009-05-05

    申请号:US11282037

    申请日:2005-11-17

    Abstract: An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.

    Abstract translation: 接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。 在一个实施例中,控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。 控制单元被配置为记录在互连上提供的标识符,该重试响应标识互连上正在进行的第二事务。 控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。 在另一个实施例中,控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应 。 控制单元还被配置为提供具有重试响应的第二事务的标识符。

    Non-blocking address switch with shallow per agent queues
    9.
    发明授权
    Non-blocking address switch with shallow per agent queues 有权
    非阻塞地址切换,每个代理队列较浅

    公开(公告)号:US07752366B2

    公开(公告)日:2010-07-06

    申请号:US12263255

    申请日:2008-10-31

    CPC classification number: G06F13/362 G06F13/4022

    Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

    Abstract translation: 在一个实施例中,开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家,并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中,系统包括多个代理,互连和耦合到多个代理和互连的开关。 在另一个实施例中,预期了一种方法。

    Retry mechanism
    10.
    发明授权
    Retry mechanism 有权
    重试机制

    公开(公告)号:US07991928B2

    公开(公告)日:2011-08-02

    申请号:US12408410

    申请日:2009-03-20

    Abstract: An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.

    Abstract translation: 接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。 在一个实施例中,控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。 控制单元被配置为记录在互连上提供的标识符,该重试响应标识互连上正在进行的第二事务。 控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。 在另一个实施例中,控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应 。 控制单元还被配置为提供具有重试响应的第二事务的标识符。

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