公开(公告)号：US09262263B2

公开(公告)日：2016-02-16

申请号：US14088867

申请日：2013-11-25

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/00

CPC classification number: G06F11/102 ,  G06F11/1064 ,  G06F12/00

Abstract: A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.

Abstract translation: 特定设备包括基于电阻的存储器件，标签随机存取存储器（RAM）和位恢复（BR）存储器。 基于电阻的存储器件被配置为存储与数据值相关联的数据值和纠错码（ECC）数据。 标签RAM被配置为存储将主存储器的存储器地址映射到高速缓冲存储器的字线的信息，其中高速缓冲存储器包括基于电阻的存储器件。 BR存储器被配置为存储与数据值相关联的附加纠错数据，其中BR存储器对应于易失性存储器设备。

公开(公告)号：US09251881B2

公开(公告)日：2016-02-02

申请号：US14040332

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00 ,  G11C7/14 ,  G11C11/15 ,  G11C29/02

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: A system and method to trim reference levels in a resistive memory is disclosed. In a particular embodiment, a resistive memory includes multiple sets of reference cells. The resistive memory also includes a reference resistance measurement circuit. A first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells. A second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells. The resistive memory also includes a trimming circuit configured to set a reference resistance based on the measured first effective resistance and the measured second effective resistance.

Abstract translation: 公开了一种在电阻性存储器中修整参考电平的系统和方法。 在特定实施例中，电阻性存储器包括多组参考单元。 电阻存储器还包括参考电阻测量电路。 第一组参考单元可由参考电阻测量电路访问，以测量对应于第一组参考单元的第一有效参考电阻。 第二组参考单元可由参考电阻测量电路访问，以测量对应于第二组参考单元的第二有效参考电阻。 电阻存储器还包括修整电路，其被配置为基于测量的第一有效电阻和所测量的第二有效电阻来设置参考电阻。

公开(公告)号：US09153307B2

公开(公告)日：2015-10-06

申请号：US14021674

申请日：2013-09-09

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16 ,  G11C7/06 ,  G11C7/14 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/14 ,  G11C11/1659 ,  G11C13/0069

Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. Each of the four MTJ cells is coupled to a distinct word line. Each of the four MTJ cells includes an MTJ element and a single transistor. The single transistor of each particular MTJ cell is configured to enable read access to the MTJ element of the particular MTJ cell.

Abstract translation: 一种装置包括一组数据单元和耦合到该组数据单元的参考单元。 参考单元包括四个磁隧道结（MTJ）单元。 四个MTJ单元中的每一个耦合到不同的字线。 四个MTJ单元中的每一个包括MTJ元件和单个晶体管。 每个特定MTJ单元的单个晶体管被配置为使得能够读取访问特定MTJ单元的MTJ元件。

公开(公告)号：US20150092469A1

公开(公告)日：2015-04-02

申请号：US14040332

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: A system and method to trim reference levels in a resistive memory is disclosed. In a particular embodiment, a resistive memory includes multiple sets of reference cells. The resistive memory also includes a reference resistance measurement circuit. A first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells. A second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells. The resistive memory also includes a trimming circuit configured to set a reference resistance based on the measured first effective resistance and the measured second effective resistance.

Abstract translation: 公开了一种在电阻性存储器中修整参考电平的系统和方法。 在特定实施例中，电阻性存储器包括多组参考单元。 电阻存储器还包括参考电阻测量电路。 第一组参考单元可由参考电阻测量电路访问，以测量对应于第一组参考单元的第一有效参考电阻。 第二组参考单元可由参考电阻测量电路访问，以测量对应于第二组参考单元的第二有效参考电阻。 电阻存储器还包括修整电路，其被配置为基于测量的第一有效电阻和所测量的第二有效电阻来设置参考电阻。

公开(公告)号：US20150070978A1

公开(公告)日：2015-03-12

申请号：US14021674

申请日：2013-09-09

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/14 ,  G11C11/1659 ,  G11C13/0069

Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. Each of the four MTJ cells is coupled to a distinct word line. Each of the four MTJ cells includes an MTJ element and a single transistor. The single transistor of each particular MTJ cell is configured to enable read access to the MTJ element of the particular MTJ cell.

Abstract translation: 一种装置包括一组数据单元和耦合到该组数据单元的参考单元。 参考单元包括四个磁隧道结（MTJ）单元。 四个MTJ单元中的每一个耦合到不同的字线。 四个MTJ单元中的每一个包括MTJ元件和单个晶体管。 每个特定MTJ单元的单个晶体管被配置为使得能够读取访问特定MTJ单元的MTJ元件。

公开(公告)号：US10311930B1

公开(公告)日：2019-06-04

申请号：US15946209

申请日：2018-04-05

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

IPC: G06F7/58 ,  G11C11/16 ,  G11C17/02 ,  H04L9/32

Abstract: One-time programming (OTP) magneto-resistive random access memory (MRAM) bit cells in a physically unclonable function (PUF) memory in breakdown to a memory state from a previous read operation to provide PUF operations is disclosed. PUF memory is configured to permanently one-time program an initial randomly generated PUF output from PUF MRAM bit cells accessed in an initial PUF read operation, to the same PUF MRAM bit cells accessed in the initial PUF read operation. In this manner, the initial PUF output is randomly generated due to process variations of the PUF MRAM bit cells to maintain an initial unpredictable memory state, but the PUF output will be reproduced for subsequent PUF read operations to the same PUF MRAM bit cells in the PUF memory array for reproducibility. The OTP of the PUF MRAM bit cells can be accomplished by applying breakdown voltage to the PUF MRAM bit cells during programming.

公开(公告)号：US10290340B1

公开(公告)日：2019-05-14

申请号：US15939484

申请日：2018-03-29

Applicant: QUALCOMM Incorporated ,  Yonsei University, University-Industry Foundation

Inventor： Seong-Ook Jung ,  Sara Choi ,  Hong Keun Ahn ,  Seung Hyuk Kang ,  Sungryul Kim

IPC: G11C11/16 ,  H01L43/08 ,  G11C7/06

Abstract: Aspects disclosed in the detailed description include offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation. The OC write operation sensing circuit is configured to sense when MTJ switching occurs in MRAM bit cell. In an example, the OC write operation sensing circuit includes a voltage sensing circuit and a sense amplifier. The voltage sensing circuit employs a capacitive-coupling effect so that the output voltage drops in response to MTJ switching for both logic ‘0’ and logic ‘1’ write operations. The sense amplifier has a single input and a single output node with an output voltage indicating when MTJ switching has occurred in the MRAM bit cell. A single input transistor and pull-up transistor are provided in the sense amplifier in one example to provide an offset-canceling effect.

公开(公告)号：US09800271B2

公开(公告)日：2017-10-24

申请号：US14852988

申请日：2015-09-14

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Sara Choi ,  Byung Kyu Song ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim ,  Seung Hyuk Kang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15

CPC classification number: H03M13/616 ,  G06F11/10 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6502

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

公开(公告)号：US09753874B2

公开(公告)日：2017-09-05

申请号：US14627318

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

IPC: G06F13/28 ,  G06F12/02 ,  G06F9/44

CPC classification number: G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

Abstract: Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

公开(公告)号：US09653183B1

公开(公告)日：2017-05-16

申请号：US15254068

申请日：2016-09-01

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Sungryul Kim ,  Jung Pill Kim

IPC: G11C29/00 ,  G11C29/18 ,  G11C11/16 ,  G11C29/12

CPC classification number: G11C29/18 ,  G11C8/12 ,  G11C11/165 ,  G11C11/1677 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/44 ,  G11C29/4401

Abstract: Shared built-in self-analysis of memory systems employing a memory array tile architecture is provided. To selectively control which memory tile among a plurality of memory tiles is accessed for a built-in self-analysis (BISA) operation, a shared BISA address issued from a shared BISA circuit includes a memory tile address. Each memory tile includes a unique fixed memory tile address that is compared to the received memory tile address of a received BISA address. If the memory tile address in the received BISA address matches the fixed memory tile address of a memory tile, the memory tile is activated to use the memory address in the BISA address to access addressed memory bit cells for analysis. Thus, if the memory system is redesigned to include additional memory tiles for increased capacity, the memory tile address size in the BISA address can be updated for addressing added memory tiles.