公开(公告)号：US20210151428A1

公开(公告)日：2021-05-20

申请号：US16686377

申请日：2019-11-18

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Je-Hsiung LAN ,  Jonghae KIM

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/16 ,  H01L23/66 ,  H01L21/02

Abstract: A semiconductor device having heterogeneous transistors integrated on a diamond substrate with a carbonized layer. An example semiconductor device generally includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a diamond substrate, a carbonized layer disposed above the diamond substrate, and a first transistor disposed above the carbonized layer, the first transistor comprising gallium nitride. The second semiconductor die is disposed above the first semiconductor die, where the second semiconductor die includes a second transistor comprising a different semiconductor material than the first transistor.

公开(公告)号：US20210098319A1

公开(公告)日：2021-04-01

申请号：US17017407

申请日：2020-09-10

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Ranadeep DUTTA ,  Jonghae KIM

IPC: H01L23/15 ,  H01L21/768 ,  H01L21/321 ,  H01L21/48 ,  H01L23/522 ,  H01L23/373 ,  H01L27/06 ,  C04B35/111 ,  C04B37/02 ,  H03H9/10 ,  H03H3/10

Abstract: Disclosed are devices and methods for semiconductor devices including a ceramic substrate. Aspects disclosed include semiconductor device including an electrical component, an alumina ceramic substrate and a substrate-film. The substrate-film is deposited on the alumina ceramic substrate. The substrate-film has a planar substrate-film surface opposite the alumina ceramic substrate. The electrical component is formed on the substrate-film surface of the substrate-film on the alumina ceramic substrate.

公开(公告)号：US20170084523A1

公开(公告)日：2017-03-23

申请号：US14861619

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Jie FU ,  Daeik Daniel KIM ,  Manuel ALDRETE ,  Chin-Kwan KIM ,  David BERDY ,  Niranjan Sunil MUDAKATTE ,  Changhan YUN ,  Je-Hsiung LAN ,  Jonghae KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01R12/79 ,  H01L2224/81

Abstract: Conventional ways of coupling die packages to external devices include providing contacts on a separate area on a printed circuit board (PCB). These PCB contacts are configured to mate with connector contacts of a connector to enable coupling with external devices. Unfortunately, the PCB contacts take up significant amount of area of the PCB. Also, the connection can suffer from parasitic losses and signal integrity can be compromised. An on-package connection is proposed to address the short comings of the conventional ways. The on-package connection enables a die package to connect directly with the connector. This removes the need to provide a separate area for PCB contacts. Also, parasitic losses are minimized and signal integrity is enhanced.

公开(公告)号：US20140354378A1

公开(公告)日：2014-12-04

申请号：US14055707

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Jonghae KIM ,  Changhan Hobie YUN ,  Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Je-Hsiung LAN ,  Robert Paul MIKULKA ,  Matthew Michael NOWAK

IPC: H03H7/01

CPC classification number: H03H7/0138 ,  H03H7/0115 ,  Y10T29/417

Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.

Abstract translation: 滤光器包括具有通过基板通孔的玻璃基板。 滤波器还包括由玻璃基板支撑的电容器。 电容器可以具有小于打印分辨率的宽度和/或厚度。 滤波器还包括衬底内的3D电感器。 3D电感器包括耦合到贯穿衬底通孔的玻璃衬底的第一表面上的第一组迹线。 3D电感器还包括耦合到贯通衬底通孔的相对端的玻璃衬底的第二表面上的第二组迹线。 玻璃基板的第二表面与玻璃基板的第一表面相对。 直通衬底通孔和迹线作为3D电感器工作。 第一组迹线和第二组迹线也可以具有小于打印分辨率的宽度和/或厚度。

公开(公告)号：US20250096116A1

公开(公告)日：2025-03-20

申请号：US18468536

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Ranadeep DUTTA

IPC: H01L23/522 ,  H01F17/00 ,  H01L23/66

Abstract: A device is described, in which the device includes a substrate. The device includes a multiturn inductor coupled to the substrate. The device also includes a patterned ground shield on a periphery of the multiturn inductor and coupled to the substrate.

公开(公告)号：US20250096093A1

公开(公告)日：2025-03-20

申请号：US18468533

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065

Abstract: A package comprising an interposer comprising a silicon substrate comprising a porous portion; and a plurality of via interconnects extending through the porous portion of the silicon substrate. The package includes a first integrated device coupled to the interposer through a first plurality of solder interconnects.

公开(公告)号：US20250096090A1

公开(公告)日：2025-03-20

申请号：US18468493

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: An integrated device comprising a die substrate comprising a porous portion; a plurality of through substrate vias extending through the porous portion of the die substrate; and a die interconnection portion coupled to the die substrate.

公开(公告)号：US20240243036A1

公开(公告)日：2024-07-18

申请号：US18153663

申请日：2023-01-12

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H03H7/01

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5223 ,  H01L23/5227 ,  H03H7/0115 ,  H03H7/0153 ,  H03H2210/025

Abstract: Disclosed is a cavity embedded tunable filter integrated with high-quality and high capacitance tuning ratio varactor, metal-insulator-metal (MIM) capacitors, and 3D inductors with through alumina ceramic substrate vias. The varactor and the MIM capacitor die is embedded into a blind alumina cavity (BAC) of an alumina ceramic substrate.

公开(公告)号：US20240021353A1

公开(公告)日：2024-01-18

申请号：US17812772

申请日：2022-07-15

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Kai LIU ,  Ranadeep DUTTA

IPC: H01F17/00 ,  H01F27/28

CPC classification number: H01F17/0013 ,  H01F27/2804 ,  H01F2027/2809

Abstract: One or more aspects include apparatuses, systems including co-spiral inductors and methods for fabricating the same. In at least one aspect, a co-spiral inductor includes a plurality of turns, each of the plurality of turns being displaced both vertically and horizontally from a next successive turn. The plurality of turns is formed from traces on different metal layers formed on a substrate. The co-spiral inductor includes a plurality of insulators configured to electrically insulate each of the plurality of turns. The co-spiral inductor includes a plurality of interconnects configured to couple each of the plurality of turns to at least one other turn.

公开(公告)号：US20240006308A1

公开(公告)日：2024-01-04

申请号：US17855492

申请日：2022-06-30

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Roy CHIU ,  Nosun PARK ,  Je-Hsiung LAN ,  Jonghae KIM

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/498 ,  H01F17/00

CPC classification number: H01L23/5227 ,  H01L23/5226 ,  H01L28/10 ,  H01L23/49827 ,  H01F17/0013 ,  H01F2017/0066 ,  H01F2017/002

Abstract: A device comprising a die substrate, a plurality of interconnects located over the die substrate, wherein the plurality of interconnects are configured to operate as an inductor, at least one magnetic layer that surrounds at least part of the plurality of interconnects; and at least one dielectric layer that surrounds the at least one magnetic layer.