公开(公告)号：US20160179595A1

公开(公告)日：2016-06-23

申请号：US14575590

申请日：2014-12-18

Applicant: Oracle International Corporation

Inventor： Michelle Wong ,  Dawei Huang ,  Thomas Wicki ,  Albert Martin

IPC: G06F11/07 ,  G06F11/10

CPC classification number: G06F11/076 ,  G06F11/0706 ,  G06F11/1004 ,  H04L1/00 ,  H04L7/00

Abstract: A serial link data monitoring apparatus for targeting a given Bit Error Rate (BER) for stable serial link data communication is disclosed. An interface unit may be configured to receive data via a serial interface, and circuitry may be configured to monitor errors in the data. The circuitry may be further configured to perform one or more first training operations in response to a determination that the number of errors detected in the data is greater than a first threshold value, and perform a second training operation in response to a determination that a number of first training operations performed in a predetermined period of time is greater than a second threshold value. An amount of time to perform the second training operation may be greater than an amount of time to perform a given one of the first training operations.

Abstract translation: 公开了一种用于针对用于稳定的串行链路数据通信的给定误码率（BER）的串行链路数据监视装置。 接口单元可以被配置为经由串行接口接收数据，并且电路可以被配置为监视数据中的错误。 电路还可以被配置为响应于确定在数据中检测到的错误的数量大于第一阈值的确定来执行一个或多个第一训练操作，并且响应于确定数字 在预定时间段内执行的第一训练操作大于第二阈值。 执行第二训练操作的时间量可以大于执行给定的第一训练操作的时间量。

公开(公告)号：US09036757B1

公开(公告)日：2015-05-19

申请号：US14493652

申请日：2014-09-23

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Jianghui Su ,  Francis Schumacher ,  Zuxu Qin ,  Dawei Huang

IPC: H04L7/00

CPC classification number: H04L7/10 ,  H04L7/0062

Abstract: Embodiments include systems and methods for applying post-cursor locking point adjustment to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). In one embodiment, a training routine is used to determine an optimal post-cursor target level. Increasing or decreasing the post-cursor target level can cause the CDR clocking to shift right or left, which can be seen as a shift of the channel impulse response with respect to the CDR sampling locations. In some implementations, the post-cursor can be locked to the determined target level. In other implementations, the determined target level can be compared to a fully-adapted post-cursor to tune adaptations performed by transmitter and/or receiver equalizers.

Abstract translation: 实施例包括用于将速度锁定点调整应用于速率时钟数据恢复（CDR）系统的系统和方法。 一些实施例在串行器/解串器（SERDES）的CDR电路的上下文中操作。 在一个实施例中，使用训练例程来确定最佳的后视标目标水平。 增加或减少后视标目标水平可能导致CDR时钟向右或向左移动，这可以被看作是信道脉冲响应相对于CDR采样位置的移位。 在一些实现中，后视标可以被锁定到确定的目标级别。 在其他实施方式中，可以将确定的目标水平与完全适配的后置光标进行比较，以调谐由发射机和/或接收机均衡器执行的适配。

公开(公告)号：US08994427B2

公开(公告)日：2015-03-31

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。