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    Layered decoder enhancement for retained sector reprocessing
    32.
    发明授权
    Layered decoder enhancement for retained sector reprocessing 有权
    用于保留扇区再处理的分层解码器增强

    公开(公告)号：US08862962B2

    公开(公告)日：2014-10-14

    申请号：US13644181

    申请日：2012-10-03

    Applicant: LSI Corporation

    Inventor： Fan Zhang ,  Jun Xiao

    IPC: H03M13/00

    CPC classification number: H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1515 ,  H03M13/6331 ,  H03M13/6343

    Abstract: A system is described for recovering data from a number of sectors, such as the sectors of a hard disk drive (HDD) disk platter, and so forth. The system receives data from the sectors via a read channel and uses a layered data decoder to recover data from the sectors. A memory is coupled with the processor and configured to retain data received from one or more of the sectors, e.g., in retained sector reprocessing (RSR) embodiments. The system is configured to update messages in different circulant layers of the data decoder's parity-check matrix. The system uses one message update order in a processing iteration, and different message update orders in subsequent reprocessing iterations. In some embodiments, layer reordering is used for RSR. In some embodiments, circulant reordering is used for RSR.

    Abstract translation: 描述了用于从诸如硬盘驱动器（HDD）盘片等的扇区的多个扇区恢复数据的系统。 系统经由读通道从扇区接收数据，并使用分层数据解码器从扇区恢复数据。 存储器与处理器耦合并且被配置为保留从一个或多个扇区接收的数据，例如在保留的扇区再处理（RSR）实施例中。 该系统被配置为更新数据解码器奇偶校验矩阵的不同循环层中的消息。 系统在处理迭代中使用一个消息更新顺序，并在后续的后处理迭代中使用不同的消息更新顺序。 在一些实施例中，层重排序用于RSR。 在一些实施例中，循环重排序用于RSR。

    SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS
    35.
    发明申请
    SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS 有权
    信号处理电路由分钟控制的FRONTEND和后端电路

    公开(公告)号：US20140181570A1

    公开(公告)日：2014-06-26

    申请号：US13724946

    申请日：2012-12-21

    Applicant: LSI CORPORATION

    Inventor： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

    IPC: G06F1/06

    CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/206

    Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

    Abstract translation: 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。

    Fixed-point processing using quantization levels based on floating-point processing
    36.
    发明授权
    Fixed-point processing using quantization levels based on floating-point processing 有权
    使用基于浮点处理的量化级的定点处理

    公开(公告)号：US08743493B1

    公开(公告)日：2014-06-03

    申请号：US13742753

    申请日：2013-01-16

    Applicant: LSI Corporation

    Inventor： Wu Chang ,  Fan Zhang ,  Ming Jin

    IPC: G11B20/10

    CPC classification number: G11B20/10268

    Abstract: An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry comprises a detector and a decoder coupled to the detector. The detector is configured to perform fixed-point detection on a digital data signal using a first set of quantization levels determined based at least in part on a result of a floating-point detection of the digital data signal. The decoder is configured to perform fixed-point decoding on an output of the detector using a second set of quantization levels determined based at least in part on a result of a floating-point decoding of the output of the detector.

    Abstract translation: 一种装置包括读通道电路和与读通道电路相关联的信号处理电路。 信号处理电路包括耦合到检测器的检测器和解码器。 检测器被配置为使用至少部分地基于数字数据信号的浮点检测的结果确定的第一组量化级对数字数据信号执行定点检测。 解码器被配置为使用至少部分地基于检测器的输出的浮点解码的结果确定的第二组量化级对检测器的输出执行定点解码。

    Load Balanced Decoding of Low-Density Parity-Check Codes
    37.
    发明申请
    Load Balanced Decoding of Low-Density Parity-Check Codes 有权
    低密度奇偶校验码负载平衡解码

    公开(公告)号：US20140122959A1

    公开(公告)日：2014-05-01

    申请号：US13664490

    申请日：2012-10-31

    Applicant: LSI CORPORATION

    Inventor： Lei Chen ,  Fan Zhang

    IPC: H03M13/13

    CPC classification number: H03M13/1111 ,  H03M13/116

    Abstract: A method for determining update candidates in a low-density parity-check decoding process includes dividing the quasi-cyclic columns into groups and identifying an update candidate in each group. One or more of the identified update candidates are then updated.

    Abstract translation: 一种用于在低密度奇偶校验解码过程中确定更新候选的方法，包括将准循环列分成组并识别每组中的更新候选。 然后更新所识别的更新候选中的一个或多个。

    MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE WITH MULTI-PENALTY
    38.
    发明申请
    MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE WITH MULTI-PENALTY 有权
    多级跑步有限公司有限公司有限责任公司

    公开(公告)号：US20140115381A1

    公开(公告)日：2014-04-24

    申请号：US13654931

    申请日：2012-10-18

    Applicant: LSI CORPORATION

    Inventor： Wu Chang ,  Razmik Karabed ,  Fan Zhang

    IPC: G06F11/16 ,  G06G7/62

    CPC classification number: G11B20/1833 ,  G11B20/10277 ,  G11B20/10287

    Abstract: Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.

    Abstract translation: 描述了基于实现不同处罚集的多级（ML）游程限制（RLL）有限状态机（FSM）来构建最大过渡运行（MTR）调制码的技术。 处理器被配置为经由读通道从硬盘驱动器（HDD）接收信息，并且使用MTR调制码从HDD恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化的马尔可夫源，并构建MTR调制码以模拟 基于具有有限转换行程长度和多级周期结构的FSM的优化马尔可夫源。 FSM在一段时间内至少提供两套不同的罚则。

    Iterative decoding using adaptive feedback
    39.
    发明授权
    Iterative decoding using adaptive feedback 有权
    使用自适应反馈的迭代解码

    公开(公告)号：US08687310B1

    公开(公告)日：2014-04-01

    申请号：US13687688

    申请日：2012-11-28

    Applicant: LSI Corporation

    Inventor： Fan Zhang ,  Jun Xiao ,  Wu Chang

    IPC: G11B5/035

    CPC classification number: G11B20/10361 ,  G11B20/10268

    Abstract: An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to: equalize a digital data signal; align the equalized digital data signal; determine a detector reliability metric based at least in part on the aligned equalized digital data signal; perform an iterative decoding process to determine a decoded digital data signal using the detector reliability metric; adjust the aligned equalized digital data signal using the decoded digital data signal; and repeat at least determining the detector reliability metric and performing the iterative decoding process using the adjusted equalized digital data signal.

    Abstract translation: 一种装置包括读通道电路和与读通道电路相关联的信号处理电路。 信号处理电路被配置为：均衡数字数据信号; 对齐均衡的数字数据信号; 至少部分地基于对准的均衡数字数据信号确定检测器可靠性度量; 执行迭代解码处理以使用检测器可靠性度量来确定解码的数字数据信号; 使用解码的数字数据信号调整对准的均衡数字数据信号; 并重复至少确定检测器可靠性度量并使用经调整的均衡数字数据信号执行迭代解码处理。

    Systems and methods for data processing using global iteration result reuse
    40.
    发明授权
    Systems and methods for data processing using global iteration result reuse 有权
    使用全局迭代结果重用的数据处理系统和方法

    公开(公告)号：US09274889B2

    公开(公告)日：2016-03-01

    申请号：US13912059

    申请日：2013-06-06

    Applicant: LSI Corporation

    Inventor： Fan Zhang ,  Shu Li ,  Jun Xiao ,  Kaitlyn T. Nguyen

    IPC: G06F11/10 ,  H03M13/11 ,  H03M13/27 ,  H03M13/00 ,  H03M13/29

    CPC classification number: G06F11/1076 ,  H03M13/1111 ,  H03M13/27 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/6331 ,  H03M13/658 ,  H03M13/6583 ,  H04L2201/06

    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for use of a detector output by a data decoder. As an example, a data processing system is discussed that includes a data detector circuit operable to provide a first detector output and a second detector output, and a combining circuit operable to combine a first input derived from the first detector output with a second input derived from the second detector output to yield a combined detector output. The combined detector output includes a unified data set element generated by combining an element of the first input with a corresponding element of the second input.

    Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于由数据解码器输出的检测器的系统和方法。 作为示例，讨论了包括可操作以提供第一检测器输出和第二检测器输出的数据检测器电路的数据处理系统，以及组合电路，其可操作以将从第一检测器输出导出的第一输入与导出的第二输入 从第二检测器输出产生组合的检测器输出。 组合的检测器输出包括通过将第一输入的元素与第二输入的相应元素组合而产生的统一数据集元素。

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