公开(公告)号：US20170214409A1

公开(公告)日：2017-07-27

申请号：US15408613

申请日：2017-01-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi KONDO ,  Akihide SAI ,  Masanori FURUTA

IPC: H03L7/099 ,  H03B5/08 ,  H04B1/38 ,  H03L7/087

CPC classification number: H03L7/099 ,  H03B5/08 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1265 ,  H03B2201/0208 ,  H03L7/087 ,  H03L7/093 ,  H03L2207/50 ,  H04B1/38

Abstract: An oscillator has an oscillator which comprises a first variable capacitor to adjust capacitance based on a first signal and a second variable capacitor to adjust capacitance, generates an oscillation signal having a frequency in accordance with the capacitance of the first variable capacitor and the second variable capacitor, an integer phase detector to detect an integer phase of the oscillation signal, a fractional phase detector to detect a fractional phase of the oscillation signal, a phase error generator to generate a fourth signal indicating a phase error of the oscillation signal, a first filter to extract the first signal in a predetermined frequency band, included in the fourth signal, and to output the first signal, and a second filter to extract the second signal in a predetermined frequency band, included in the fourth signal, and to output the second signal.

公开(公告)号：US20170194972A1

公开(公告)日：2017-07-06

申请号：US15462288

申请日：2017-03-17

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Akihide SAI ,  Masanori FURUTA ,  Tetsuro ITAKURA ,  Satoshi KONDO ,  Hidenori OKUNI ,  Tuan thanh TA

IPC: H03L7/099 ,  H04L7/033 ,  H03K5/24 ,  H03K21/02 ,  G04F10/00 ,  H03L7/093

CPC classification number: H03L7/099 ,  G04F10/005 ,  H03K5/24 ,  H03K5/26 ,  H03K21/02 ,  H03L7/06 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L2207/50 ,  H04L7/033

Abstract: A time to digital converter has a counter to measure the number of cycles of a first signal, a first phase difference detector to generate a phase difference signal having a pulse width corresponding to a phase difference, a first capacitor to be charged with an electric charge, a second capacitor including capacitance N times the capacitance of the first capacitor, the N being a real number larger than 1, a comparator to compare a charge voltage of the first capacitor and a charge voltage of the second capacitor, a first charge controller to continue to charge the second capacitor until the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more, and a first phase difference arithmetic unit to operate the phase difference between the first signal and the second signal.

公开(公告)号：US20200064186A1

公开(公告)日：2020-02-27

申请号：US16292813

申请日：2019-03-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tuan Thanh TA ,  Akihide SAI ,  Hidenori OKUNI ,  Satoshi KONDO

IPC: G01J1/44 ,  G01S17/10 ,  G01S7/486

Abstract: According to one embodiment, an electronic apparatus includes a first avalanche photo diode, a second avalanche photo diode, a first pulse circuit, a second pulse circuit, a first waveform shaping circuit, a second waveform shaping circuit and an adder. The first pulse circuit is configured to shape a signal of the first avalanche photo diode to a first pulse. The second pulse circuit is configured to shape a signal of the second avalanche photo diode to a second pulse. The first waveform shaping circuit is configured to shape the first pulse to a third pulse having a narrower frequency bandwidth than that of the first pulse. The second waveform shaping circuit is configured to shape the second pulse to a fourth pulse having a narrower frequency bandwidth than that of the second pulse. The adder is configured to add the third pulse and the fourth pulse.

公开(公告)号：US20190068216A1

公开(公告)日：2019-02-28

申请号：US15920611

申请日：2018-03-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Akihide SAI ,  Satoshi KONDO ,  Kentaro YOSHIOKA ,  Tetsuro ITAKURA

IPC: H03M3/00

CPC classification number: H03M3/458 ,  G04F10/00 ,  G04F10/005 ,  H03M1/60

Abstract: An analog-to-digital converter has a switched capacitor comprising a capacitor to perform charging and discharging by switching a switch, the switched capacitor varying a charge amount of the capacitor in accordance with a frequency of an oscillation signal in accordance with a differential signal between an input signal and a feedback signal, capacitance of the capacitor, and a predetermined bias voltage, a feedback signal generator to generate the feedback signal based on an output signal of the switched capacitor, and a digital converter to generate a digital signal by digital conversion of the input signal based on the oscillation signal.

公开(公告)号：US20180062826A1

公开(公告)日：2018-03-01

申请号：US15461809

申请日：2017-03-17

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hidenori OKUNI ,  Akihide SAI ,  Masanori FURUTA ,  Satoshi KONDO ,  Tuan Thanh TA

IPC: H04L7/00 ,  H04B1/16

CPC classification number: H04L7/0079 ,  H04B1/16 ,  H04L7/0331 ,  H04L7/0332

Abstract: A radio communication device has an analog control loop unit to generate an analog control signal, a digital control loop unit which has a frequency determined with the frequency of a reference signal and a predetermined frequency setting code signal, a voltage controlled oscillator to generate the voltage control oscillation signal, a data slicer to generate a digital signal obtained by digitally demodulating the reception signal, an automatic offset controller to generate a correction signal, a setting code adjuster to adjust the frequency setting code signal, based on the correction signal, and a direct-current level adjuster to adjust a direct-current level of the digital control signal, based on the correction signal. The data slicer compares the digital control signal adjusted by the direct-current level adjuster, with the threshold value.

公开(公告)号：US20170214517A1

公开(公告)日：2017-07-27

申请号：US15409918

申请日：2017-01-19

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi KONDO ,  Akihide SAI ,  Masanori FURUTA

IPC: H04L7/033 ,  H04B1/16 ,  H04L7/00 ,  H03L7/08 ,  H03L7/085

CPC classification number: H04B1/16 ,  G06F1/3278 ,  H03L7/08 ,  H03L7/0802 ,  H03L2207/50

Abstract: A receiver has an oscillator to output an oscillation signal, a receiver to perform reception processing of a reception signal, a phase frequency detector to output a first signal in response to a phase and a frequency of the oscillation signal so as to generate a second signal indicating a reference phase, a differentiator to generate a third signal being a difference between the first signal and the second signal, an oscillator controller to generate a fourth signal for controlling a phase and a frequency of the oscillator, a phase initializer to output an initialization signal for synchronizing a phase of the second signal with a phase of the first signal, a trigger signal generator to output a trigger signal indicating timing with which the phase initializer outputs the initialization signal, and a power supply controller to control whether to supply a power supply voltage.

公开(公告)号：US20160380759A1

公开(公告)日：2016-12-29

申请号：US15189236

申请日：2016-06-22

Applicant: Kabushiki Kaisha Toshiba

Inventor： Satoshi KONDO ,  Akihide SAI ,  Masanori FURUTA

IPC: H04L7/033

CPC classification number: H04L7/0332 ,  H03L7/081 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0334

Abstract: A phase locked loop has an integer phase detector to detect an integer phase by measuring a cycle number, a fractional phase detector to detect a fractional phase of smaller than one cycle between a reference signal and the oscillation signal, a frequency error generator to generate a frequency error signal between the reference signal and the oscillation signal, a glitch corrector to correct the frequency error signal to generate and output a glitch-corrected signal and the frequency error signal, a phase error generator to generate a phase error by integrating an output signal of the glitch corrector, an oscillator controller to control an oscillation frequency of the oscillation signal, and a synchronous detector to detect whether a phase of the reference signal and a phase of the oscillation signal are in an phase-lock state, and to stop detection of the integer phase when the phase-lock state is detected.

Abstract translation: 锁相环具有通过测量周期数来检测整数相位的整数相位检测器，用于检测参考信号和振荡信号之间小于一个周期的分数相位的分数相位检测器，产生 参考信号和振荡信号之间的频率误差信号，毛刺校正器，用于校正频率误差信号以产生和输出毛刺校正信号和频率误差信号;相位误差发生器，用于通过对输出信号进行积分来产生相位误差 干扰校正器的振荡器控制器，用于控制振荡信号的振荡频率的振荡器控制器，以及用于检测参考信号的相位和振荡信号的相位是否处于锁相状态的同步检测器，并且停止检测 检测相位锁定状态时的整数相位。

公开(公告)号：US20160173303A1

公开(公告)日：2016-06-16

申请号：US15048297

申请日：2016-02-19

Applicant: Kabushiki Kaisha Toshiba

Inventor： Akihide SAI ,  Masanori Furuta ,  Tetsuro Itakura

IPC: H04L27/16 ,  H04L27/32 ,  H04L27/227

CPC classification number: H04L27/16 ,  H04L27/227 ,  H04L27/32

Abstract: A wireless communication device has an analog control loop circuitry that generates an analog control signal to adjust a phase of a voltage controlled oscillation signal, in accordance with a phase of a reception signal, a digital control loop circuitry that generates a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and having a phase opposite to a phase of the analog control signal, a voltage controlled oscillator that generates the voltage controlled oscillation signal, on the basis of the analog control signal and the digital control signal, and a data slicer that generates a digital signal obtained by digital demodulation of the reception signal, on the basis of a comparison result of the digital control signal and a predetermined threshold value.

Abstract translation: 无线通信设备具有模拟控制环路电路，其根据接收信号的相位产生模拟控制信号以调整受压控振荡信号的相位，数字控制环路电路产生数字控制信号，该数字控制环路具有 频率由参考信号的频率和预定的频率设定码信号确定，并且具有与模拟控制信号的相位相反的相位，基于模拟控制信号产生压控振荡信号的压控振荡器 和数字控制信号，以及数据限幅器，其基于数字控制信号的比较结果和预定的阈值，生成通过接收信号的数字解调获得的数字信号。

公开(公告)号：US20150130647A1

公开(公告)日：2015-05-14

申请号：US14538212

申请日：2014-11-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tetsuro ITAKURA ,  Masanori FURUTA ,  Akihide SAI ,  Junya MATSUNO ,  Yohei HATAKEYAMA

IPC: H03M1/00 ,  H03M1/06 ,  H03F3/16 ,  G06G7/184 ,  H03F3/45

CPC classification number: H03M1/002 ,  H03F3/45273 ,  H03F2200/267 ,  H03F2200/91 ,  H03F2203/45034 ,  H03M1/00 ,  H03M1/0604 ,  H03M1/12 ,  H03M1/365

Abstract: In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.

Abstract translation: 在一个实施例中，电流放大器电路包括第一晶体管，第一电阻器，第二晶体管，第二电阻器，第一无源元件和控制电路。 第一晶体管具有第一端子，第二端子和控制端子。 第一电阻器的一端连接到第一晶体管的第一端子。 第二晶体管具有第一端子，第二端子和控制端子。 第二电阻器的一端连接到第二晶体管的第一端子。 第一无源元件连接在第一晶体管的第一端子和第二晶体管之间。 控制电路控制第一晶体管和第二晶体管的控制端的电压中的至少一个，使得第一电阻的另一端的电压变得等于第二电阻的另一端的电压。