公开(公告)号：US20160276015A1

公开(公告)日：2016-09-22

申请号：US15170606

申请日：2016-06-01

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract translation: 存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。 检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目 。 检测逻辑确定对存储器件的行的访问次数是否超过阈值。 响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。

公开(公告)号：US20160254036A1

公开(公告)日：2016-09-01

申请号：US14926860

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/10 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0605 ,  G06F3/0683 ,  G06F13/4022 ,  G06F13/4282 ,  G06F13/4295 ,  G06F15/7807 ,  G11C7/1003 ,  G11C7/1021 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  Y02D10/14 ,  Y02D10/151

Abstract: Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.

Abstract translation: 内存灵活的命令寻址。 存储器件的实施例包括动态随机存取存储器（DRAM）; 以及与DRAM耦合的系统元件，所述系统元件包括用于控制DRAM的存储器控​​制器。 DRAM包括存储体，总线，总线包括用于接收命令的多个引脚和逻辑，其中逻辑提供用于第一类型的命令的总线的共享操作和接收的第二类型的命令 在第一组引脚上。

公开(公告)号：US09299400B2

公开(公告)日：2016-03-29

申请号：US13631781

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C13/00 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4078

CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4078

Abstract: A memory controller issues a targeted refresh command in response to detection by a distributed detector. A memory device includes detection logic that monitors for a row hammer event, which is a threshold number of accesses to a row within a time threshold that can cause data corruption to a physically adjacent row (a “victim” row). The memory device sends an indication of the row hammer event to the memory controller. In response to the row hammer event indication, the memory controller sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract translation: 存储器控制器响应于分布式检测器的检测器发出目标刷新命令。 存储器装置包括检测逻辑，该检测逻辑监视行敲击事件，该行敲击事件是对时间阈值内可能导致数据损坏到物理相邻行（“受害者”行）的行的阈值数量。 存储器件向存储器控制器发送行锤事件的指示。 响应于行锤事件指示，存储器控制器将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

公开(公告)号：US09152257B2

公开(公告)日：2015-10-06

申请号：US13730642

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains ,  Derek M. Conrow ,  Aaron Martin

IPC: H03K3/012 ,  G06F3/041 ,  H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0008 ,  G06F3/041 ,  G06F3/0412 ,  H03K19/0005 ,  H03K19/017509 ,  H03K19/017545

Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

Abstract translation: 输出驱动器包括被配置为接通上拉电路和下拉电路以提供传输线路上的逻辑低电平的输出阻抗的控制逻辑。 输出驱动器包括一个可变上拉电阻。 控制逻辑被配置为将上拉电路接通到第一阻抗值，以驱动传输线上的逻辑高电平。 控制逻辑被配置为将上拉电路接通到第二阻抗值，并且接通下拉电路以提供输出阻抗以驱动传输线上的逻辑低电平。 可替代地，该系统可以被配置为用于将逻辑高的上拉电路和下拉电路的组合打开，其中下拉电路被接通为逻辑低电平。

公开(公告)号：US20240222347A1

公开(公告)日：2024-07-04

申请号：US18148338

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Kuljit S. Bains ,  Wilfred Gomes ,  Don Douglas Josephson ,  Surhud V. Khare ,  Christopher Philip Mozak ,  Randy B. Osborne ,  Pushkar Ranade ,  Abhishek Anil Sharma

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/16 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).

公开(公告)号：US11966286B2

公开(公告)日：2024-04-23

申请号：US17715771

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Rajat Agarwal ,  Jongwon Lee

IPC: G06F11/10 ,  G11C11/4096

CPC classification number: G06F11/1044 ,  G06F11/1072 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US11335395B2

公开(公告)日：2022-05-17

申请号：US17062420

申请日：2020-10-02

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  Christopher P. Mozak ,  James A. McCall ,  Akshith Vasanth ,  Bill Nale

IPC: G11C11/4072 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/406

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US11314589B2

公开(公告)日：2022-04-26

申请号：US16875642

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Rajat Agarwal ,  Jongwon Lee

IPC: G06F11/10 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US11056179B2

公开(公告)日：2021-07-06

申请号：US16737666

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Chong J. Zhao ,  James A. McCall ,  Shigeki Tomishima ,  George Vergis ,  Kuljit S. Bains

IPC: G11C29/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/408 ,  H01L27/108

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

公开(公告)号：US10949296B2

公开(公告)日：2021-03-16

申请号：US15681387

申请日：2017-08-20

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G11C29/42 ,  G11C29/44 ,  G11C11/40 ,  G11C29/04 ,  G11C29/56

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.