公开(公告)号：US11335395B2

公开(公告)日：2022-05-17

申请号：US17062420

申请日：2020-10-02

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  Christopher P. Mozak ,  James A. McCall ,  Akshith Vasanth ,  Bill Nale

IPC: G11C11/4072 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/406

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.