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公开(公告)号：US20160170829A1
公开(公告)日：2016-06-16
申请号：US14953459
申请日：2015-11-30
CPC分类号： G06F11/1004 , G06F9/3867 , G06F11/1008 , G06F11/3024 , G06F11/3409
摘要： A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.
摘要翻译： 一种从流水线处理器中的数据的错误检查中离域的方法。 在第一数据的第一位置生成第一检查数据。 第二位置接收第一数据和第一检查数据。 在第一数据上产生第二检查数据，并且将第一检查数据与第二位置处的第二检查数据进行比较。 从第一数据产生第二数据，并且在第二位置处对第二数据生成第三检查数据。 在第二位置处的第二数据上生成第三检查数据，并且将第二数据传送到第三位置。 第三个检查数据被传送到第四个位置。 在第二数据上产生第四检查数据，并将其传送到第四位置。 第四个检查数据和第三个检查数据在第四个位置进行比较。
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公开(公告)号：US11269651B2
公开(公告)日：2022-03-08
申请号：US16565946
申请日：2019-09-10
发明人： Michael Klein , Nicol Hofmann , Cedric Lichtenau , Osher Yifrach
摘要： A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.
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公开(公告)号：US20210034325A1
公开(公告)日：2021-02-04
申请号：US16527138
申请日：2019-07-31
摘要： A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.
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公开(公告)号：US20200341839A1
公开(公告)日：2020-10-29
申请号：US16397107
申请日：2019-04-29
发明人： Stefan Payer , Michael Klein , Nicol Hofmann , Cedric Lichtenau
摘要： Aspects include parsing, by a computer system, a design file of an integrated circuit including a plurality of stages to extract a plurality of inputs and outputs of a plurality of latches. The computer system can sort the latches based on latch locations in the stages and build a plurality of ordered vectors of signals before and after the latches based on the sorting. The computer system can build a plurality of parity vectors for each of the ordered vectors of signals before and after the latches, build a latch bank for each of the parity vectors before the latches, and build a parity vector comparison to detect a parity failure based on comparing the parity vectors after the latches with an output of the latch bank.
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公开(公告)号：US10275391B2
公开(公告)日：2019-04-30
申请号：US15412429
申请日：2017-01-23
发明人： Nicol Hofmann , Michael Klein , Cédric Lichtenau
摘要： A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.
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公开(公告)号：US20190018653A1
公开(公告)日：2019-01-17
申请号：US15649406
申请日：2017-07-13
CPC分类号： G06F7/5443 , G06F5/01 , G06F7/49
摘要： Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.
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公开(公告)号：US20180210859A1
公开(公告)日：2018-07-26
申请号：US15412429
申请日：2017-01-23
发明人： Nicol Hofmann , Michael Klein , Cédric Lichtenau
CPC分类号： G06F15/80 , G06F7/52 , G06F9/3001 , G06F9/30014 , G06F9/3887 , G06F15/7867
摘要： A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.
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公开(公告)号：US09928135B2
公开(公告)日：2018-03-27
申请号：US14953459
申请日：2015-11-30
CPC分类号： G06F11/1004 , G06F9/3867 , G06F11/1008 , G06F11/3024 , G06F11/3409
摘要： A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.
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公开(公告)号：US09734126B1
公开(公告)日：2017-08-15
申请号：US15289388
申请日：2016-10-10
发明人： James R. Cuffney , Nicol Hofmann , Michael Klein , Petra Leber , Cédric Lichtenau , Silvia M. Mueller , Timothy J. Slegel
CPC分类号： G06F15/7867 , G06F7/57 , G06F11/3644 , G06F11/3648
摘要： A system and method for controlling post-silicon configurable instruction behavior are provided. For example, the method includes receiving data related to a compute circuit. The method also includes detecting a data pattern in the data. The method further includes determining that the data pattern is a special case that the compute circuit may handle improperly. The method also includes selecting a value from a post-silicon configurable data set based on the detected data. Further, the method includes changing a behavior of the compute circuit to produce a different output result based on the value selected from the post-silicon configurable data set.
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公开(公告)号：US09697074B2
公开(公告)日：2017-07-04
申请号：US14567344
申请日：2014-12-11
CPC分类号： G06F11/1004 , G06F9/3867 , G06F11/1008 , G06F11/3024 , G06F11/3409
摘要： A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.
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