公开(公告)号：US20160139830A1

公开(公告)日：2016-05-19

申请号：US14547639

申请日：2014-11-19

Applicant: International Business Machines Corporation

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Michael F. Fee ,  Pak-Kin Mak ,  Arthur J. O'Neill ,  Robert J. Sonnelitter, III

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/283

Abstract: A computing device is provided and includes a plurality of nodes. Each node includes multiple chips and a node controller at which the multiple chips are assignable to logical partitions. Each of the multiple chips includes processors and a memory unit configured to handle local memory operations originating from the processors. The node controller includes a dynamic memory relocation (DMR) mechanism configured to move data having a DMR storage increment address relative to a local one of the memory units without interrupting a processing of the data by at least one of the logical partitions. During movement of the data by the DMR mechanism, the memory units are disabled from handling the local memory operations matching the DMR storage increment address and the node controller handles the local memory operations matching the DMR storage increment address.

Abstract translation: 提供了一种计算设备并且包括多个节点。 每个节点包括多个芯片和一个节点控制器，多个芯片可以分配到逻辑分区。 多个芯片中的每一个包括处理器和被配置为处理源自处理器的本地存储器操作的存储器单元。 节点控制器包括动态存储器重定位（DMR）机制，其被配置为移动具有相对于存储器单元中的本地存储器单元的DMR存储增量地址的数据，而不会中断至少一个逻辑分区对数据的处理。 在通过DMR机制移动数据期间，禁止存储器单元处理与DMR存储增量地址匹配的本地存储器操作，并且节点控制器处理与DMR存储器增量地址匹配的本地存储器操作。

公开(公告)号：US20160124854A1

公开(公告)日：2016-05-05

申请号：US14533579

申请日：2014-11-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Garrett M. Drapala ,  Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Gary E. Strait

IPC: G06F12/08 ,  G06F13/42

CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0842 ,  G06F13/4221 ,  G06F2212/271 ,  G06F2212/604

Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

Abstract translation: 一种方法，计算机程序产品和系统，用于维持包括两个或多个顺序排列的存储器的数据流的正确排序，所述数据流被移动到目的地存储器设备，所述两个或多个顺序排序的存储器至少包括第一 存储和第二存储，其中第一存储被目的地存储设备拒绝。 计算机实现的方法包括将第一存储发送到目的地存储设备。 将条件请求发送到目的地存储器设备以批准将第二存储发送到目的地存储器设备，该条件请求取决于第一存储器的成功完成。 响应于接收到对应于第一商店的拒绝响应，第二商店被取消。

公开(公告)号：US09292445B2

公开(公告)日：2016-03-22

申请号：US14501437

申请日：2014-09-30

Applicant: International Business Machines Corporation

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Rebecca M. Gott ,  Pak-kin Mak ,  Vijayalakshmi Srinivasan ,  Craig R. Walters

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F12/0811 ,  G06F12/0831 ,  G06F2212/283 ,  G06F2212/621

Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.

Abstract translation: 实施例涉及用于计算机的对称多处理器（SMP）的非数据包含的一致（NIC）目录。 一个方面包括确定SMP的第一处理器节点的多级高速缓存结构中的最高级缓存的第一逐出条目。 另一方面包括确定NIC目录未满。 另一方面包括确定最高级别高速缓存的第一驱逐条目是由多级缓存结构中的较低级别高速缓存所拥有的。 另一方面包括，基于NIC目录不是完整的，并且基于由较低级别高速缓存所拥有的最高级缓存的第一次驱逐条目，将最高级别高速缓存的第一次驱逐条目的地址安装在 NIC目录中的第一个新条目。 另一方面包括使最高级缓存中的第一个逐出条目无效。

公开(公告)号：US20150261638A1

公开(公告)日：2015-09-17

申请号：US14501676

申请日：2014-09-30

Applicant: International Business Machines Corporation

Inventor： Garrett M. Drapala ,  Gary E. Strait

IPC: G06F11/273

CPC classification number: G11C29/04 ,  G06F11/273 ,  G11C29/12 ,  G11C29/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52

Abstract: Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.

公开(公告)号：US20150058569A1

公开(公告)日：2015-02-26

申请号：US14501437

申请日：2014-09-30

Applicant: International Business Machines Corporation

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Rebecca M. Gott ,  Pak-kin Mak ,  Vijayalakshmi Srinivasan ,  Craig R. Walters

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F12/0811 ,  G06F12/0831 ,  G06F2212/283 ,  G06F2212/621

Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.

Abstract translation: 实施例涉及用于计算机的对称多处理器（SMP）的非数据包含的一致（NIC）目录。 一个方面包括确定SMP的第一处理器节点的多级高速缓存结构中的最高级缓存的第一逐出条目。 另一方面包括确定NIC目录未满。 另一方面包括确定最高级别高速缓存的第一驱逐条目是由多级缓存结构中的较低级别高速缓存所拥有的。 另一方面包括，基于NIC目录不是完整的，并且基于由较低级别高速缓存所拥有的最高级别缓存的第一次驱逐条目，将最高级别高速缓存的第一次驱逐条目的地址安装在 NIC目录中的第一个新条目。 另一方面包括使最高级缓存中的第一个逐出条目无效。

公开(公告)号：US20130339623A1

公开(公告)日：2013-12-19

申请号：US13746882

申请日：2013-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Timothy C. Bronson ,  Garrett M. Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0815 ,  G06F12/0859

Abstract: A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.