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公开(公告)号：US20190244084A1
公开(公告)日：2019-08-08
申请号：US16206687
申请日：2018-11-30
Inventor： Yong Cheol Peter CHO , Young-Su KWON
Abstract: The processing element may include a first multiplexer selecting one of a first value stored in a first memory and a second value stored in a second memory, a second multiplexer selecting one of a first data input signal and an output value of the first multiplexer, a third multiplexer selecting one of the output value of the first multiplexer and a second data input signal, a multiplier multiplying an output value of the second multiplexer by an output value of the third multiplexer, a fourth multiplexer for selecting one of the output value of the second multiplexer and an output value of the multiplier, and a third memory storing an output value of the fourth multiplexer.
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公开(公告)号：US20190114236A1
公开(公告)日：2019-04-18
申请号：US16022334
申请日：2018-06-28
Inventor： Jin Ho HAN , Min-Seok CHOI , Young-Su KWON
Abstract: A network on-chip may include a master circuit that outputs write data or receives read data, a slave circuit that stores the write data or outputs the read data, a master network interface circuit that generates a first error correction code associated with the write data, a slave network interface circuit that generates a second error correction code associated with the read data, and an on-chip network circuit that transmits the write data and the first error correction code to the slave network interface circuit or transmits the read data and the second error correction code to the master network interface circuit, the master network interface circuit decodes the read data and the second error correction code and requests the read data again or generates a first fault signal, and the slave network interface circuit decodes the write data and the first error correction code and requests the write data again or generates a second fault signal.
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公开(公告)号：US20180159699A1
公开(公告)日：2018-06-07
申请号：US15823104
申请日：2017-11-27
Inventor： Jeongmin YANG , Sung Weon KANG , Young-Su KWON
IPC: H04L12/40 , H04L12/863 , H04L12/413
CPC classification number: H04L12/40032 , G05B2219/25032 , H04L12/4135 , H04L47/6245 , H04L2012/40215
Abstract: Provided are Controller Area Network (CAN) controller and a data transmission method using the same. The CAN controller includes a receiver, a reception First in First out (FIFO) memory, a transmission FIFO memory, and a transmitter. The receiver is configured to analyze reception information received from a CAN bus according to a set protocol. The reception FIFO memory is configured to store the reception information to be overwritten on previously stored reception information based on identification data of the reception information and a bus load. The transmission FIFO memory is configured to store the transmission information to be overwritten on previously stored transmission information based on identification data of the transmission information and a processor load of the processor. The transmitter is configured to set the protocol and transmit the transmission information stored in the transmission FIFO memory to the CAN bus.
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公开(公告)号：US20170262011A1
公开(公告)日：2017-09-14
申请号：US15432588
申请日：2017-02-14
Inventor： Young-Su KWON , Kyung Jin BYUN , Nak Woong EUM
CPC classification number: G06F11/1608 , G06F1/06 , G06F1/12 , G06F11/0724 , G06F11/1641 , G06F11/1675 , G06F11/1679
Abstract: Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.
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公开(公告)号：US20240163139A1
公开(公告)日：2024-05-16
申请号：US18506544
申请日：2023-11-10
Inventor： Young-deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO , Jae-Woong CHOI
CPC classification number: H04L25/03057 , G06F13/16 , H04L25/0272 , G06F2213/16
Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.
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Patent Agency Ranking
公开(公告)号：US20230115549A1
公开(公告)日：2023-04-13
申请号：US17903112
申请日：2022-09-06
Inventor： Yi-Gyeong KIM , Young-deuk JEON , Young-Su KWON , Jin-Ho HAN
Abstract: Disclosed herein is an apparatus for receiving a strobe signal. The apparatus may include an amplifier for amplifying a strobe signal input thereto, an offset generator for controlling the setting of a threshold for detecting a preamble signal by generating an offset for the amplifier, and a preamble detector for detecting a first preamble signal occurring at a point at which the amplified strobe signal is equal to or greater than the threshold and turning off the offset generator when the first preamble signal is detected.
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公开(公告)号：US20220180162A1
公开(公告)日：2022-06-09
申请号：US17544224
申请日：2021-12-07
Inventor： Jin-Ho HAN , Young-Su KWON , Mi-Young LEE , Joo-Hyun LEE , Yong-Cheol CHO
IPC: G06N3/063
Abstract: Disclosed herein is an AI accelerator. The AI accelerator includes processors, each performing a deep-learning operation using multiple threads; and a cache memory including an L0 instruction cache for providing instructions to the processors and an L1 cache mapped to the multiple areas of mapped memory.
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38.发明申请公开(公告)号：US20220172029A1
公开(公告)日：2022-06-02
申请号：US17536536
申请日：2021-11-29
Inventor： In San JEON , Young-Su KWON , Chun-Gi LYUH , Young-deuk JEON , MIN-HYUNG CHO , Jin Ho HAN
Abstract: Disclosed is a simplified sigmoid function circuit which includes a first circuit that performs a computation on input data based on a simplified sigmoid function when a sign of a real region of the input data is positive, a second circuit that performs the computation on the input data based on the simplified sigmoid function when the sign of the real region of the input data is negative, and a first multiplexer that selects and output one of an output of the first circuit and an output of the second circuit, based on the sign of the input data. The simplified sigmoid function is obtained by transforming a sigmoid function of a real region into a sigmoid function of a logarithmic region and performing a variational transformation for the sigmoid function of the logarithmic region.
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公开(公告)号：US20220164308A1
公开(公告)日：2022-05-26
申请号：US17523615
申请日：2021-11-10
Inventor： Chun-Gi LYUH , Min-Seok CHOI , Young-Su KWON , Jin Ho HAN
Abstract: Disclosed is a processor according to the present disclosure, which includes processing elements, a kernel data memory that provides a kernel data set to the processing elements, a data memory that provides an input data set to the processing elements, and a controller that provides commands to the processing elements, and a first processing element among the processing elements delays a first command received from the controller and first input data received from the data memory for a delay time, and then transfers the delayed first command and the delayed first input data to a second processing element, and the controller adjusts the delay time.
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公开(公告)号：US20210182222A1
公开(公告)日：2021-06-17
申请号：US17119387
申请日：2020-12-11
Inventor： Jin Ho HAN , Min-Seok CHOI , Young-Su KWON
IPC: G06F13/16 , G06F13/28 , G06F12/1081 , G06F12/02
Abstract: Disclosed is a cache including a dataflow controller for transmitting first data to a first processor and receiving second data from the first processor, an external direct memory access (DMA) controller for receiving the first data from an external memory to transmit the first data to the dataflow controller and receiving the second data from the dataflow controller to transmit the second data to the external memory, a scratchpad memory for storing the first data or the second data transmitted between the dataflow controller and the external DMA controller, a compression/decompression device for compressing data to be transmitted from the scratchpad memory to the external memory and decompressing data transmitted from the external memory to the scratchpad memory, and a transfer state buffer for storing transfer state information associated with data transfer between the dataflow controller and the external DMA controller.
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