Method for detecting array substrate of display panel

    公开(公告)号:US10373537B2

    公开(公告)日:2019-08-06

    申请号:US15122579

    申请日:2015-10-20

    Abstract: A method for detecting a display panel is disclosed. The display panel comprises an array substrate for driving an electroluminescent device. The array substrate comprises pixel electrodes arranged in an array and an array of pixel switches for driving the pixel electrodes. The method comprises the steps of: S1, applying a first driving signal to a manufactured array substrate, monitoring a first voltage on the pixel electrode; S2, forming a second electrode on each of the pixel electrodes of the array substrate; S3, applying a second driving signal to the array substrate formed with the second electrode, monitoring a second current flowing through the second electrode. The pixel electrode is one of the cathode and the anode of the electroluminescent device, the second electrode is the other one of the cathode and the anode of the electroluminescent device.

    NOR gate circuit, shift register, array substrate and display apparatus

    公开(公告)号:US10027329B2

    公开(公告)日:2018-07-17

    申请号:US15304751

    申请日:2015-10-29

    Inventor: Zhongyuan Wu

    Abstract: Provided are an NOR gate circuit, a shift register, an array substrate and a display apparatus, wherein the NOR gate circuit comprises a first inverter and a second inverter, each of the first inverter and the second inverter having an input terminal (VIN), a high voltage terminal (VGH), a low voltage terminal (VGL) and an output terminal (VOUT), the output terminal (VOUT) of the first inverter being connected to the high voltage terminal (VGH) of the second inverter, and wherein at least one of the first inverter and the second inverter comprises: a first transistor (T1; T5) having a gate connected to a first node (VA), a first electrode connected to the high voltage terminal (VGH) and a second electrode connected to the output terminal (VOUT), a first capacitor (C1; C2) having a first terminal connected to the first node (VA) and a second terminal connected to the output terminal (VOUT), a pulling-up module being configured to pull up a potential at the first node (VA) by a potential at the high voltage terminal (VGH) in a case where the high voltage terminal (VGH) is at a high level, and a pulling-down module being configured to pull down a potential at the first node (VA) and a potential at the output terminal (VOUT) by a potential at the low voltage terminal (VGL) under a control of a signal received by the input terminal (VIN). The threshold loss existing in the NOR gate circuit formed by an Oxide TFT can be eliminated.

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