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公开(公告)号：US20190221588A1
公开(公告)日：2019-07-18
申请号：US15580240
申请日：2017-06-23
Inventor： Tongshang Su , Jun Cheng , Ce Zhao , Bin Zhou , Dongfang Wang , Guangcai Yuan
IPC: H01L27/12 , G09G3/3283 , G09G3/3291 , G02F1/133
Abstract: The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises at least a first region and a second region. A thickness of an active layer of the thin film transistor in the first region is different from that of an active layer of the thin film transistor in the second region. A ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region.
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32.发明申请公开(公告)号：US20190157308A1
公开(公告)日：2019-05-23
申请号：US16030825
申请日：2018-07-09
Inventor： Yuankui Ding , Guangcai Yuan , Ce Zhao , Bin Zhou , Jun Cheng , Zhaofan Liu , Yingbin Hu , Yongchao Huang
IPC: H01L27/12 , H01L29/786 , H01L21/027 , G03F7/16 , G03F7/20 , G03F7/26 , G03F7/42 , G03F7/038
Abstract: A method of manufacturing an array substrate assembly, an array substrate assembly manufactured by the method, and a display panel including the array substrate assembly are disclosed. The method includes: providing a substrate, the substrate having a first region as a preset semiconductor-removed region, and a second region as a remaining region; forming, in the first region of the substrate, a semiconductor removing layer corrodible by a corrosive solution; and forming a semiconductor layer on the substrate formed with the semiconductor removing layer, so that the semiconductor layer covers the semiconductor removing layer.
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公开(公告)号：US10217955B2
公开(公告)日：2019-02-26
申请号：US15814690
申请日：2017-11-16
Inventor： Leilei Cheng , Jun Bao , Dongfang Wang , Ce Zhao
Abstract: A method for manufacturing a display panel, and a display device are disclosed. The method for manufacturing a display panel includes: providing a TFT substrate; dispersing graphene and metal nanowires in a hydrophilic solvent to form a hydrophilic conductive ink; applying the hydrophilic conductive ink onto the TFT substrate to form a composite electrode layer; forming, on the composite electrode layer, a pixel defining layer having a plurality of openings at least partially exposing the composite electrode layer; applying hydrophilic organic ink into the plurality of openings of the pixel defining layer to form an organic layer; drying the composite electrode layer and the organic layer to form a first electrode and an organic light emitting structure; and forming a second electrode on the organic light emitting structure and the pixel defining layer.
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34.发明申请公开(公告)号：US20170162604A1
公开(公告)日：2017-06-08
申请号：US15436141
申请日：2017-02-17
Applicant: BOE Technology Group Co., Ltd.
Inventor： Ce Zhao , Chunsheng Jiang , Guangcai Yuan
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1225 , H01L21/02565 , H01L21/426 , H01L29/24 , H01L29/66969 , H01L29/78606 , H01L29/78618 , H01L29/7869
Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The method includes forming a gate electrode, a gate insulating layer, a metal oxide semiconductor (MOS) active layer, a source electrode and a drain electrode on a substrate. The MOS active layer includes forming a pattern layer of indium oxide series binary metal oxide including a first pattern directly contacting with the source electrode and the drain electrode. An insulating layer formed over the source electrode and the drain electrode acts as a protection layer, the pattern layer of indium oxide series binary metal oxide is implanted with metal doping ions by using an ion implanting process, and is annealed, so that the indium oxide series binary metal oxide of the third pattern is converted into the indium oxide series multiple metal oxide to form the MOS active layer.
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公开(公告)号：US20250024705A1
公开(公告)日：2025-01-16
申请号：US18701887
申请日：2023-04-28
Inventor： Liusong Ni , Cheng Xu , Chen Xu , Ce Zhao , Ming Wang , Yingbin Hu , Ning Liu , Jiawen Song , Junlin Peng , Wei He
IPC: H10K59/121 , H10K59/12 , H10K59/123
Abstract: A display substrate is provided, including: pixel units on a base substrate; and a first conductive layer, a buffer layer, a semiconductor layer, a first insulation layer, and a second conductive layer which are arranged on the base substrate in a direction away from the base substrate. The display substrate further includes at least one conductive via hole passing through at least the first insulation layer, and at least one conductive plug through which the second conductive portion is electrically connected to the first conductive portion. The first conductive portion includes first and second conductive sub-portions, an orthographic projection of the first conductive sub-portion on the base substrate at least partially overlaps with that of the at least one conductive via hole on the base substrate, and in a third direction, a thickness of the first conductive sub-portion is greater than that of the second conductive sub-portion.
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Patent Agency Ranking
公开(公告)号：US11616113B2
公开(公告)日：2023-03-28
申请号：US16966847
申请日：2020-01-03
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
IPC: H01L27/32 , G02F1/1362 , H01L51/56
Abstract: A method of manufacturing a display substrate includes: providing a base substrate; and forming a base insulating layer, a first conductive layer and an interlayer insulating layer that are sequentially stacked on top of one another at a side of the base substrate. The first conductive layer includes at least one break face, the base insulating layer includes a portion extending outward with respect to each of the at least one break face, and the break face and the corresponding portion extending outward constitute an unevenness portion having a stepped shape. The interlayer insulating layer covers at least the unevenness portion(s). Forming the interlayer insulating layer, includes: forming a first insulating sub-layer and a second insulating sub-layer that are sequentially stacked on top of one another; and forming one of the first insulating sub-layer and the second insulating sub-layer by curing a flowable insulating material.
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公开(公告)号：US11315783B2
公开(公告)日：2022-04-26
申请号：US16487552
申请日：2019-02-20
Inventor： Yuankui Ding , Heekyu Kim , Liangchen Yan , Ce Zhao , Bin Zhou , Yingbin Hu , Wei Song , Dongfang Wang
Abstract: A method of fabricating a display substrate is provided. The method includes forming a conductive layer on a base substrate; and performing a chemical vapor deposition process to form an oxide layer on a side of an exposed surface of the conductive layer away from the base substrate, the exposed surface of the conductive layer including copper, the oxide layer formed to include an oxide of a target element M. The chemical vapor deposition process is performed using a mixture of a first reaction gas including oxygen and a second reaction gas including the target element M, at a reaction temperature in a range of 200 Celsius degrees to 280 Celsius degrees. A mole ratio of oxygen element to the target element M in the mixture of the first reaction gas and the second reaction gas is in a range of 40:1 to 60:1.
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公开(公告)号：US11309428B2
公开(公告)日：2022-04-19
申请号：US16706160
申请日：2019-12-06
Inventor： Wei Song , Ce Zhao , Yuankui Ding , Ming Wang , Jun Liu , Yingbin Hu , Wei Li , Liusong Ni
IPC: H01L29/78 , H01L29/786 , H01L27/12 , H01L27/32
Abstract: The present disclosure provides a transistor and a manufacturing method thereof, a display substrate and a display device. The transistor includes: a base structure; an active layer on the base structure; and a gate electrode, a source electrode and a drain electrode that are all located on a side of the active layer distal to the base structure. The active layer includes a first region corresponding to an orthographic projection of the gate electrode on the base structure and a second region outside the orthographic projection. A surface of the base structure in contact with the active layer in the first region is not in the same plane as a surface of the base structure in contact with the active layer in the second region. The active layer in the first region has substantially the same thickness as a thickness of the active layer in the second region.
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公开(公告)号：US20210335950A1
公开(公告)日：2021-10-28
申请号：US16476474
申请日：2018-09-21
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Dongfang Wang , Bin Zhou , Ce Zhao , Tongshang Su , Yuankui Ding , Ming Wang
IPC: H01L27/32 , G09G3/3233 , H01L51/56
Abstract: The present disclosure provides a pixel unit, a method of manufacturing the same, and an array substrate. The pixel unit includes: a driving transistor, a switching transistor, and a light emitting element on a substrate; wherein the driving transistor has an input electrode electrically connected to a first power supply terminal and an output electrode electrically connected to a first terminal of the light emitting element; the switching transistor has an input electrode electrically connected to a data line, a control electrode electrically connected to a scan line, and an output electrode electrically connected to a gate electrode of the driving transistor; wherein the switching transistor and the driving transistor have different threshold voltages.
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公开(公告)号：US20210335946A1
公开(公告)日：2021-10-28
申请号：US16620653
申请日：2019-03-22
Inventor： Wei Song , Liangchen Yan , Ce Zhao , Heekyu Kim , Yuankui Ding , Leilei Cheng , Yingbin Hu , Wei Li , Yang Zhang
Abstract: The present disclosure relates to a pixel structure. The pixel structure may include a base substrate; a first insulating island on a side of the base substrate; a first electrode on a side of the first insulating island opposite front the base substrate; a second electrode on the base substrate and at a peripheral area of the first insulating island; an active layer electrically connected to the first electrode and the second electrode; a second insulating layer on a side of the active layer opposite from the base substrate; a gate electrode on a side of the second insulating layer opposite from the base substrate; and a third insulating layer on a side of the gate electrode opposite from the base substrate.
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