公开(公告)号：US20050077917A1

公开(公告)日：2005-04-14

申请号：US10605603

申请日：2003-10-13

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone

IPC分类号： G06F15/78 ,  H03K19/177

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

摘要翻译： 一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。 需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB1，FB2，FB3）。 程序员包含将RLA分割成位于两个存储区域SR1，SR2之间的功能区域FR的软件（144）。 然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。 当程序员使用下一个功能块重新配置功能区域并且重新配置用于接收下一个功能块的输出的一个存储区域时，从当前功能块传递到下一个功能块的数据被保存在 其他存储区域。

公开(公告)号：US20050013527A1

公开(公告)日：2005-01-20

申请号：US10604410

申请日：2003-07-18

申请人： Gary Doyle ,  Kenneth Goodnow ,  Riyon Harding ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

发明人： Gary Doyle ,  Kenneth Goodnow ,  Riyon Harding ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

IPC分类号： G02B6/43 ,  G02B6/12 ,  G02B6/26

CPC分类号： G02B6/43

摘要： Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.

摘要翻译： 公开了一种集成电路，其包括附接到至少一个发射机和接收机的多个核心，嵌入在集成电路的有线电平内的光传输网络，并且其中发射机和接收机在网络上发送和接收数据。 还公开了一种在包括多个核心和光路的集成电路的集成电路内传输信号的方法，从多个光路中选择用于发送数据的光路，以及在所选择的光路上发送数据。 还公开了一种集成电路，其包括光传输网络，多个核心和多个控制器，所有三个可操作地彼此连接。

公开(公告)号：US06405234B2

公开(公告)日：2002-06-11

申请号：US08927950

申请日：1997-09-11

申请人： Sebastian Ventrone

发明人： Sebastian Ventrone

IPC分类号： G06F900

CPC分类号： G06F9/46 ,  G06F9/462

摘要： A processing system executing multiple programs and operating under control of an operating system, comprising a processor unit which includes a dispatch/decode unit under control of the operating system for dispatching and decoding instructions of the multiple programs, the instructions each including a program ID. The processor unit further comprises a plurality of execution units, each separately selectable by the operating system for receiving any of the instructions of the multiple programs from the dispatch/decode unit, wherein one of the execution units is executing an instruction from one of the multiple programs while another of the execution units is executing an instruction from another one of the multiple programs. The processor unit also comprises a retirement unit storing results of executed ones of the instructions uniquely in response to each program ID.

摘要翻译： 一种执行多个程序并在操作系统的控制下操作的处理系统，包括处理器单元，其包括在操作系统的控制下的调度/解码单元，用于分配和解码多个程序的指令，每个指令包括程序ID。 处理器单元还包括多个执行单元，每个执行单元可由操作系统单独选择，用于从调度/解码单元接收多个程序的任何指令，其中执行单元之一执行来自多个 程序，而另一个执行单元正在执行来自多个程序中的另一个的指令。 处理器单元还包括退出单元，该退出单元响应于每个节目ID唯一地存储执行的指令的结果。

公开(公告)号：US5357617A

公开(公告)日：1994-10-18

申请号：US796194

申请日：1991-11-22

申请人： Gordon T. Davis ,  Sebastian Ventrone

发明人： Gordon T. Davis ,  Sebastian Ventrone

IPC分类号： G06F9/38 ,  G06F9/00 ,  G06F9/40

CPC分类号： G06F9/3802 ,  G06F9/3851

摘要： A hybrid pipelined processor and associated processing methods are described for separately handling substantially concurrently in a time division manner multiple program instruction threads. The hybrid architecture includes an instruction fetch unit, an instruction decode unit and an execution unit. The execution unit includes multiple sets of register files each of which contains the working contents for a corresponding one of a plurality n of instruction threads. Timing and control circuitry is coupled to each of the principal processor components for controlling the timing and sequence of operations on instructions from the plurality n of instruction threads such that multiple instruction threads are separately handled substantially concurrently. Corresponding hybrid processing methods for such a single pipelined processor are also discussed.

摘要翻译： 描述了混合流水线处理器和相关联的处理方法，用于以时分方式基本上同时处理多个程序指令线程。 混合架构包括指令提取单元，指令解码单元和执行单元。 执行单元包括多组寄存器文件，每个寄存器文件包含多个n个指令线程中相应的一个的工作内容。 定时和控制电路耦合到每个主处理器组件，用于根据来自多个指令线程的指令来控制操作的定时和顺序，使得多个指令线程基本上同时被单独处理。 还讨论了这种单流水线处理器的相应的混合处理方法。

公开(公告)号：US20080068073A1

公开(公告)日：2008-03-20

申请号：US11937559

申请日：2007-11-09

申请人： Nancy Pratt ,  Sebastian Ventrone

发明人： Nancy Pratt ,  Sebastian Ventrone

IPC分类号： H03K5/00

CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

摘要： A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

摘要翻译： 数字系统 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

公开(公告)号：US20070288787A1

公开(公告)日：2007-12-13

申请号：US11836827

申请日：2007-08-10

申请人： Nancy Pratt ,  Sebastian Ventrone

发明人： Nancy Pratt ,  Sebastian Ventrone

IPC分类号： G06F1/00

CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

摘要： A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

公开(公告)号：US20070220468A1

公开(公告)日：2007-09-20

申请号：US11752035

申请日：2007-05-22

申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

公开(公告)号：US20070188249A1

公开(公告)日：2007-08-16

申请号：US11353516

申请日：2006-02-14

申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

IPC分类号： H03B5/12

CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。

公开(公告)号：US20070075736A1

公开(公告)日：2007-04-05

申请号：US11371833

申请日：2006-03-09

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

IPC分类号： H03K19/177

CPC分类号： H03K19/177

摘要： A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

公开(公告)号：US20070028151A1

公开(公告)日：2007-02-01

申请号：US11161330

申请日：2005-07-29

申请人： Laura Miller ,  Nancy Pratt ,  Sebastian Ventrone

发明人： Laura Miller ,  Nancy Pratt ,  Sebastian Ventrone

IPC分类号： G06F11/00

CPC分类号： G06F9/462 ,  G06F9/4843

摘要： A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.

摘要翻译： 一种用于在单个集成电路上支持同时操作操作系统的方法和系统。 该系统包括管理指令的执行的监控操作系统（SOS），每个指令可在一个操作系统下执行; 寄存器分组成多组寄存器，每组寄存器保持一个操作系统的标识; 以及调度器，其能够分派附加到所述指令的指令和标签，所述标签识别所述操作系统中的一个以及在所述操作系统下执行的指令以访问所述寄存器之一。 当执行指令时，使用一个或多个寄存器，并且被包括在多组寄存器的单组中。 单一集合维护由标签识别的操作系统的标识，并且一个或多个寄存器中的每一个包括与标签相匹配的标识符。