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    FPGA POWERUP TO KNOWN FUNCTIONAL STATE
    1.
    发明申请
    FPGA POWERUP TO KNOWN FUNCTIONAL STATE 失效
    FPGA电源到已知的功能状态

    公开(公告)号：US20080030226A1

    公开(公告)日：2008-02-07

    申请号：US11869921

    申请日：2007-10-10

    申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

    发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

    摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

    摘要翻译： 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
    2.
    发明申请
    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE 有权
    基于充电储存装置的可能性确定使用数据保留装置的相对数量

    公开(公告)号：US20070258305A1

    公开(公告)日：2007-11-08

    申请号：US11279639

    申请日：2006-04-13

    申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

    发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

    IPC分类号： G11C7/00

    CPC分类号： G06F12/121 ,  G06F12/122

    摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

    摘要翻译： 公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

    Coding of FPGA and standard cell logic in a tiling structure
    5.
    发明申请
    Coding of FPGA and standard cell logic in a tiling structure 审中-公开
    FPGA和标准单元逻辑在平铺结构中的编码

    公开(公告)号：US20060190908A1

    公开(公告)日：2006-08-24

    申请号：US11375891

    申请日：2006-03-15

    申请人： Stanislav Bajuk ,  Jack Smith ,  Sebastian Ventrone

    发明人： Stanislav Bajuk ,  Jack Smith ,  Sebastian Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5068

    摘要： A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

    摘要翻译： 一种存储和修改寄存器传输语言（RTL）的方法和系统，描述逻辑类型。 在声明信号互连时，基于信号互连的类型为信号互连定义了寄存器传输语言的语言扩展。语言扩展允许不同的信号互连类型，例如与现场可编程门阵列（例如， FPGA）和标准单元存储在相同的文件阵列层次结构中，这种存储有助于改变逻辑类型，从而最终导致集成电路（IC）更小（使用更多的标准单元）或更灵活（使用更多的FPGA 在物理设计周期内执行从一个RTL类型到另一个RTL类型的转换，其中在屏蔽最终芯片设计之前执行组件（信息）的布线，定时和布局。

    Data acknowledgment using impedance mismatching
    7.
    发明申请
    Data acknowledgment using impedance mismatching 失效
    使用阻抗失配的数据确认

    公开(公告)号：US20050076170A1

    公开(公告)日：2005-04-07

    申请号：US10680756

    申请日：2003-10-07

    申请人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

    发明人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4269

    摘要： A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer between a first core and a second core within the semiconductor device. The transmitter is adapted to send a signal over the transmission line to the receiver adapted to receive the signal. The receiver is further adapted to create an impedance mismatch to indicate that the second core is unable to transfer the data. The transmitter is adapted to detect the impedance mismatch.

    摘要翻译： 一种用于控制半导体器件上的数据流的结构和相关方法。 在半导体器件内形成发射器，接收器和传输线。 发射器，接收器和传输线适于控制半导体器件内的第一芯和第二芯之间的数据传输。 发射机适于通过传输线路将信号发送到适于接收信号的接收机。 接收机还适于产生阻抗失配以指示第二核心不能传送数据。 发射机适用于检测阻抗失配。

    Dynamic energy management
    8.
    发明授权
    Dynamic energy management 有权
    动态能源管理

    公开(公告)号：US08549330B2

    公开(公告)日：2013-10-01

    申请号：US12641578

    申请日：2009-12-18

    申请人： Paul Niekrewicz ,  Pascal A. Nsame ,  Aydin Suren ,  Sebastian Ventrone

    发明人： Paul Niekrewicz ,  Pascal A. Nsame ,  Aydin Suren ,  Sebastian Ventrone

    IPC分类号： G06F1/00

    CPC分类号： G06F1/26 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

    摘要： A computer system with reliable dynamic energy management includes a thread synchronized energy configurator, the thread synchronized energy configurator extending an instruction decoder of the computer system and the thread synchronized energy configurator is disposed to append an energy configuration field including energy configuration bits to pipeline control bits of instructions in the instruction decoder, a thread synchronized dynamic frequency shifter (DFS), the thread synchronized DFS disposed to set control signals indicative of a frequency shift both per thread and per pipeline, and a thread synchronized general purpose register (GPR) super scaler, wherein the GPR super scaler is disposed to optimize thread operation based upon the set control signals.

    摘要翻译： 具有可靠的动态能量管理的计算机系统包括螺纹同步的能量配置器，延伸计算机系统的指令解码器的线程同步能量配置器和线程同步的能量配置器被设置为将包括能量配置位的能量配置字段附加到流水线控制位 指令解码器中的指令，线程同步动态移频器（DFS），线程同步DFS被设置为设置指示每线程和每个线路的频移的控制信号，以及线程同步通用寄存器（GPR）超级缩放器 其中，GPR超级定标器被设置为基于所设置的控制信号来优化线程操作。

    Dynamic Energy Managment
    9.
    发明申请
    Dynamic Energy Managment 有权
    动态能源管理

    公开(公告)号：US20110154064A1

    公开(公告)日：2011-06-23

    申请号：US12641578

    申请日：2009-12-18

    申请人： Paul Niekrewicz ,  Pascal A. Nsame ,  Aydin Suren ,  Sebastian Ventrone

    发明人： Paul Niekrewicz ,  Pascal A. Nsame ,  Aydin Suren ,  Sebastian Ventrone

    IPC分类号： G06F1/00

    CPC分类号： G06F1/26 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

    摘要： A computer system with reliable dynamic energy management includes a thread synchronized energy configurator, the thread synchronized energy configurator extending an instruction decoder of the computer system and the thread synchronized energy configurator is disposed to append an energy configuration field including energy configuration bits to pipeline control bits of instructions in the instruction decoder, a thread synchronized dynamic frequency shifter (DFS), the thread synchronized DFS disposed to set control signals indicative of a frequency shift both per thread and per pipeline, and a thread synchronized general purpose register (GPR) super scaler, wherein the GPR super scaler is disposed to optimize thread operation based upon the set control signals.

    摘要翻译： 具有可靠的动态能量管理的计算机系统包括螺纹同步的能量配置器，延伸计算机系统的指令解码器的线程同步能量配置器和线程同步的能量配置器被设置为将包括能量配置位的能量配置字段附加到流水线控制位 指令解码器中的指令，线程同步动态移频器（DFS），线程同步DFS被设置为设置指示每线程和每个线路的频移的控制信号，以及线程同步通用寄存器（GPR）超级缩放器 其中，GPR超级定标器被设置为基于所设置的控制信号来优化线程操作。

    TEST SYSTEM FOR INTEGRATED CIRCUITS
    10.
    发明申请
    TEST SYSTEM FOR INTEGRATED CIRCUITS 失效
    集成电路测试系统

    公开(公告)号：US20080091994A1

    公开(公告)日：2008-04-17

    申请号：US11955433

    申请日：2007-12-13

    申请人： Alvar Dean ,  Sebastian Ventrone

    发明人： Alvar Dean ,  Sebastian Ventrone

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2893 ,  G01R1/0408 ,  G01R31/318505 ,  G01R31/31932

    摘要： A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing Chips are disconnected from further testing and passing or failing chips are recorded.

    摘要翻译： 测试板包括用于连接到待测试的多个集成电路芯片的多个插座。 板上的测试控制装置打开至少一个测试引擎，同时测试多个芯片。 检查电路通过将芯片的输出相互比较或与金色芯片进行比较来验证每个芯片的功能。 失败的芯片与进一步的测试断开连接，并记录通过或失败的芯片。