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    Wiring optimizations for power
    1.
    发明申请
    Wiring optimizations for power 有权
    电力接线优化

    公开(公告)号：US20050262463A1

    公开(公告)日：2005-11-24

    申请号：US11176712

    申请日：2005-07-07

    申请人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

    发明人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

    IPC分类号： G06F17/50 ,  H01L21/82 ,  G06F9/45 ,  H03K19/0175

    CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

    摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

    摘要翻译： 电气布线结构及其设计方法。 该方法识别具有第一线和第二线的至少一个线对。 第二根线已经是三态的，也可以是三态的。 线对可以具有不小于预定或用户选择的最小相同方向切换概率的每时钟周期的相同方向的切换概率。 或者，线对可以具有不小于预定或用户选择的最小相反方向切换概率的每时钟周期的相反方向切换概率。 第一线和第二线满足至少一个数学关系，涉及：第一线和第二线之间的间隔; 以及第一线和第二线的公共行程长度。

    Split I/O circuit for performance optimization of digital circuits
    2.
    发明授权
    Split I/O circuit for performance optimization of digital circuits 失效
    分离式I / O电路，用于数字电路的性能优化

    公开(公告)号：US06269468B1

    公开(公告)日：2001-07-31

    申请号：US09260453

    申请日：1999-03-02

    申请人： Alvar Dean ,  Patrick E. Perry ,  Sebastian Ventrone

    发明人： Alvar Dean ,  Patrick E. Perry ,  Sebastian Ventrone

    IPC分类号： G06F1750

    CPC分类号： G06F17/505 ,  G06F2217/78

    摘要： A logic circuit device and circuit design methodology includes a “split-book” logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using “split” book designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the strand may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting. Then, the output buffers may then be connected together according to criticality of the path and net capacitive load they are driving. Different split book input/output circuit combinations may be attempted during the design phase until an optimal tradeoff between power optimization and performance is reached.

    摘要翻译： 逻辑电路器件和电路设计方法包括具有不同有源器件尺寸的“分离式”逻辑电路设计，其输出用于连接关键和非关键数字电路路径。 通过使用具有独立输入和输出级的“拆分”书籍设计，更好的硅利用率，功耗优化和性能结果。 这是因为每个拆分书都设计有多个输出缓冲区，可以配置为最佳地驱动关键路径和非关键路径。 在设计的功率/性能优化阶段期间，首先确定设计的时序关键路径，每个路径都以其自身为基础进行优化。 首先，可以通过在书的输入端口上的更强的驱动来改进链的输入阶段。 仅链接到关键路径的输入端口已更新。 其他输入引脚保持默认设置。 然后，输出缓冲器然后可以根据它们正在驱动的路径和净电容负载的关键性被连接在一起。 可以在设计阶段尝试不同的分页输入/输出电路组合，直到达到功率优化和性能之间的最佳权衡。

    TEST SYSTEM FOR INTEGRATED CIRCUITS
    3.
    发明申请
    TEST SYSTEM FOR INTEGRATED CIRCUITS 失效
    集成电路测试系统

    公开(公告)号：US20080091994A1

    公开(公告)日：2008-04-17

    申请号：US11955433

    申请日：2007-12-13

    申请人： Alvar Dean ,  Sebastian Ventrone

    发明人： Alvar Dean ,  Sebastian Ventrone

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2893 ,  G01R1/0408 ,  G01R31/318505 ,  G01R31/31932

    摘要： A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing Chips are disconnected from further testing and passing or failing chips are recorded.

    摘要翻译： 测试板包括用于连接到待测试的多个集成电路芯片的多个插座。 板上的测试控制装置打开至少一个测试引擎，同时测试多个芯片。 检查电路通过将芯片的输出相互比较或与金色芯片进行比较来验证每个芯片的功能。 失败的芯片与进一步的测试断开连接，并记录通过或失败的芯片。

    WIRING OPTIMIZATIONS FOR POWER
    4.
    发明申请
    WIRING OPTIMIZATIONS FOR POWER 有权
    电力接线优化

    公开(公告)号：US20080074147A1

    公开(公告)日：2008-03-27

    申请号：US11952544

    申请日：2007-12-07

    申请人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

    发明人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

    IPC分类号： H03K19/00 ,  G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

    摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

    摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有不小于预先选择的最小相同方向切换概率phi，SD，MIN或/或具有相同方向的切换概率，每时钟周期 每个时钟周期的相反方向切换概率Φ不小于预先选择的最小相对方向切换概率φi，MIN 。 第一线和第二线满足至少一个数学关系，其涉及公平和平坦，其中，W SPACING 被定义为 第一线和第二线，以及公共被定义为第一线和第二线的公共行程长度。

    FPGA POWERUP TO KNOWN FUNCTIONAL STATE
    6.
    发明申请
    FPGA POWERUP TO KNOWN FUNCTIONAL STATE 失效
    FPGA电源到已知的功能状态

    公开(公告)号：US20080030226A1

    公开(公告)日：2008-02-07

    申请号：US11869921

    申请日：2007-10-10

    申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

    发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

    摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

    摘要翻译： 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
    7.
    发明申请
    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE 有权
    基于充电储存装置的可能性确定使用数据保留装置的相对数量

    公开(公告)号：US20070258305A1

    公开(公告)日：2007-11-08

    申请号：US11279639

    申请日：2006-04-13

    申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

    发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

    IPC分类号： G11C7/00

    CPC分类号： G06F12/121 ,  G06F12/122

    摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

    摘要翻译： 公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

    Coding of FPGA and standard cell logic in a tiling structure
    10.
    发明申请
    Coding of FPGA and standard cell logic in a tiling structure 审中-公开
    FPGA和标准单元逻辑在平铺结构中的编码

    公开(公告)号：US20060190908A1

    公开(公告)日：2006-08-24

    申请号：US11375891

    申请日：2006-03-15

    申请人： Stanislav Bajuk ,  Jack Smith ,  Sebastian Ventrone

    发明人： Stanislav Bajuk ,  Jack Smith ,  Sebastian Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5068

    摘要： A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

    摘要翻译： 一种存储和修改寄存器传输语言（RTL）的方法和系统，描述逻辑类型。 在声明信号互连时，基于信号互连的类型为信号互连定义了寄存器传输语言的语言扩展。语言扩展允许不同的信号互连类型，例如与现场可编程门阵列（例如， FPGA）和标准单元存储在相同的文件阵列层次结构中，这种存储有助于改变逻辑类型，从而最终导致集成电路（IC）更小（使用更多的标准单元）或更灵活（使用更多的FPGA 在物理设计周期内执行从一个RTL类型到另一个RTL类型的转换，其中在屏蔽最终芯片设计之前执行组件（信息）的布线，定时和布局。